Clocking Circuit for CMOS Charge Pump Leakage Reduction
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Solution Overview
Problem
CMOS cross-coupled charge pumps face inefficiencies in voltage boosting due to substantial reversion loss and leakage, leading to deviations in output voltage and switching ripple, particularly in semiconductor integrated circuits requiring high voltages.
Innovation Solution
A charge pump design incorporating a voltage multiplier core with cross-coupled CMOS devices and a clocking circuit that generates synchronized non-overlapping and overlapping clock signals, which are voltage boosted to minimize leakage and prevent 'dead zones' in output currents, thereby maintaining stable output voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional clocking circuits are used to drive CMOS cross-coupled charge pumps, then the charge pumps can operate, but substantial reversion loss and leakage occur leading to output voltage deviation and switching ripple
Solution Approach 1:
The clocking circuit dynamically adjusts clock signal timing parameters including rise time, fall time, pulse width, and phase relationships. The circuit transitions between different clocking modes (non-overlapping and overlapping) based on operating conditions to optimize performance and minimize leakage losses while maintaining output voltage stability.
Solution Approach 2:
The invention changes multiple clock signal parameters simultaneously including rise time, fall time, pulse width, and phase differences. By optimizing these parameters, the circuit minimizes leakage current in the charge pump while preventing output voltage deviation and switching ripple, thereby resolving the contradiction between energy loss and voltage stability.
2Productivity
If clock signals with fast transitions are used to improve switching speed, then productivity increases, but leakage losses increase due to incomplete discharge of capacitive nodes
Solution Approach 1:
The clocking circuit dynamically controls the rise and fall times of clock signals to match the charging and discharging requirements of capacitive nodes. By adjusting transition speeds rather than using fixed fast edges, the circuit maintains high switching productivity while ensuring complete discharge of capacitive nodes to minimize leakage losses.
Solution Approach 2:
The circuit applies preliminary anti-action by ensuring complete discharge of capacitive nodes before the next charging cycle begins. The clock signal timing is designed to fully discharge nodes through controlled transition times, preventing the buildup of residual charges that would cause leakage losses, while maintaining adequate switching speed through optimized pulse widths.
3Loss of energy
If non-overlapping clock signals are used to reduce leakage, then leakage loss decreases, but dead zones appear in output current causing voltage drops
Solution Approach 1:
The clocking circuit dynamically switches between non-overlapping and overlapping clock signal modes depending on operational requirements. During phases where leakage minimization is critical, non-overlapping signals are used; during phases requiring continuous output current, overlapping signals eliminate dead zones. This dynamic adaptation resolves the contradiction between leakage reduction and current continuity.
Solution Approach 2:
The invention employs periodic switching between different clocking schemes (non-overlapping and overlapping) to balance leakage minimization and output current continuity. By alternating between modes in a periodic fashion, the circuit achieves average leakage reduction while maintaining sufficient output current continuity through the overlapping phases.
4Power
If overlapping clock signals are used to eliminate dead zones, then output current continuity improves, but leakage losses increase
Solution Approach 1:
The clocking circuit dynamically adjusts the degree of overlap between clock phases based on load conditions and voltage requirements. When continuous output current is prioritized, greater overlap is applied; when leakage minimization is prioritized, overlap is reduced. This dynamic control resolves the contradiction between current continuity and leakage loss by adapting to real-time operational needs.
Data Source
AI summary
A charge pump includes a voltage multiplier core and a clocking circuit. The voltage multiplier core includes first and second cross-coupled CMOS devices, first and second output CMOS devices, a first capacitive node coupled between the first cross-coupled CMOS device and the first output CMOS device, and a second capacitive node coupled between the second cross-couple CMOS device and the second output CMOS device. The clocking circuit configured to control the first and second output CMOS devices to inhibit a drop in respective output voltages there from, while simultaneously controlling the first and second cross-coupled CMOS device and input voltages applied to the first and second capacitive nodes to minimize leakage from the first and second capacitive nodes.