Semiconductor Memory Device Erasing Voltage Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in maintaining operational reliability due to variations in the erasing process across memory cells with different physical characteristics, such as varying PS diameters, which can lead to uneven erasing rates and potential deterioration of memory cell transistors.
Innovation Solution
The semiconductor memory device employs a control unit that applies distinct voltages to word lines based on the PS diameter of memory cell transistors during the erasing operation. This approach ensures that memory cells with smaller PS diameters receive higher voltages to prevent excessive erasing, while those with larger diameters receive lower voltages to avoid under-erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform voltage is applied to all word lines during erasing operation, then the control is simple, but memory cells with different PS diameters experience uneven erasing rates leading to operational reliability deterioration
Solution Approach 1:
The patent applies different voltages to different word lines based on their position in the stack, which corresponds to memory cells with different PS diameters. Specifically, a first voltage is applied to a first word line and a second voltage (different from the first) is applied to a second word line, creating localized quality adjustments that compensate for physical variations in memory cell transistors at different locations.
Solution Approach 2:
The patent changes the voltage parameter applied to word lines during erasing operations based on the position of memory cells. By adjusting the voltage level according to the PS diameter characteristics of memory cells at different word lines, the system optimizes erasing effectiveness and prevents operational reliability deterioration.
2Manufacturing precision
If higher voltage is applied to memory cells with smaller PS diameters, then excessive erasing is prevented, but the control mechanism becomes more complex
Solution Approach 1:
The patent implements local quality control by applying different voltages to different word lines corresponding to memory cells with different PS diameters. This ensures that each region receives the appropriate voltage level needed for precise erasing control, preventing both excessive and insufficient erasing.
Solution Approach 2:
The patent employs dynamic voltage adjustment during erasing operations, where the voltage applied to word lines is varied based on the specific erasing stage and the characteristics of memory cells being erased. This dynamic approach allows for adaptive control that maintains precision while managing complexity.
Data Source
AI summary
A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.