Variable Voltage Electron Discharge for Memory Array Verify Recovery

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Solution Overview

Problem

Current non-volatile memory storage devices face inefficiencies in the verify recovery operation, particularly in discharging electrons from memory arrays, which can lead to effective channel boosting loss and hot carrier injection, affecting subsequent programming operations.

Innovation Solution

The proposed solution involves eliminating the seeding phase and performing array cleaning and bitline separation in parallel with the verify recovery phase, using variable voltages to efficiently discharge electrons and stabilize bitlines, thereby optimizing the array state for the next pulse operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a series of array cleaning operations is performed sequentially to discharge electrons from the memory array during verify recovery, then complete electron discharge is achieved, but pulse preparation time is excessive

Engineering Contradiction:

Improveelectron discharge completenessVSAvoidpulse preparation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing bitline separation and stabilization operations before the main array cleaning operations. Specifically, bitlines are separated and stabilized to their final voltages during the verify recovery phase, before the actual electron discharge cleaning begins. This preliminary preparation reduces the time needed for subsequent operations and prevents channel boosting loss by establishing proper bitline states in advance.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements continuity of useful action by overlapping and parallelizing multiple operations. The verify recovery phase, array cleaning operations, and bitline stabilization are performed concurrently rather than sequentially. This continuous execution of multiple useful actions simultaneously reduces the total pulse preparation time while maintaining complete electron discharge from the memory array.

Inventive Principle:

Principle #20Continuity of useful action

2Productivity

If variable voltages are applied to discharge electrons from the memory array, then electron discharge efficiency is improved, but voltage control complexity increases

Engineering Contradiction:

Improveelectron discharge efficiencyVSAvoidvoltage control complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies local quality by using different voltage levels on different bitlines and wordlines during the array cleaning operation. Specifically, variable voltages are applied to different segments of the memory array based on their specific discharge requirements. This localized voltage control optimizes electron discharge efficiency for each region while managing overall voltage control complexity through systematic voltage assignment.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements parameter changes by dynamically adjusting voltage levels during the verify recovery and array cleaning phases. The voltage parameters are changed from initial programming voltages to recovery voltages, and then to cleaning voltages in a controlled sequence. This systematic parameter transformation improves electron discharge efficiency while keeping voltage control complexity manageable through predefined voltage transition patterns.

Inventive Principle:

Principle #35Parameter changes

3Loss of time

If the seeding phase is eliminated and array cleaning is performed in parallel with verify recovery, then pulse preparation time is reduced, but risk of undesired charge injection increases

Engineering Contradiction:

Improvepulse preparation timeVSAvoidcharge injection control

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The patent applies segmentation by dividing the memory array into different regions and applying different voltage schemes to different segments during the parallel verify recovery and array cleaning operation. This segmented approach allows selective electron discharge in specific regions while maintaining proper voltage levels in other regions, thereby reducing pulse preparation time without increasing the risk of undesired charge injection through controlled regional differentiation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements feedback by continuously monitoring the voltage levels and electron discharge status during the parallel verify recovery and array cleaning operations. The verify results provide feedback on which cells have achieved the desired programming level, and this information is used to adjust the array cleaning voltages in real-time. This feedback mechanism ensures complete electron discharge while preventing undesired charge injection, maintaining reliability despite the eliminated seeding phase.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11139036B2Using variable voltages to discharge electrons from a memory array during verify recovery operations

Publication Date: 2021.10.05 INTEL NDTM US LLC

AI summary

Provided are an apparatus, memory device, and method for using variable voltages to discharge electrons from a memory array during verify recovery operations. In response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, a memory controller concurrently applies voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons and applies voltages to the bitlines to perform bitline stabilization.