Semiconductor Memory Device Program Loop Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face challenges in achieving optimal threshold voltage distribution during program operations, leading to inefficiencies and potential deterioration in memory cell performance as the number of program loops increases.
Innovation Solution
The semiconductor memory device employs a method where memory cells are categorized into groups based on program loops, applying program inhibit and allowable voltages to bit lines accordingly, thereby controlling the threshold voltage distribution and reducing RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional program operation is performed without categorizing memory cells into groups, then the program operation can be implemented with simple control logic, but the threshold voltage distribution deteriorates and RC delay increases as the number of program loops increases
Solution Approach 1:
The patent divides memory cells into multiple groups based on their program loop count and applies different voltage conditions to each group. Specifically, memory cells are segmented into a first group (programmed in odd program loops) and a second group (programmed in even program loops), allowing differentiated voltage control that optimizes threshold voltage distribution while managing RC delay effects
Solution Approach 2:
The patent dynamically adjusts the voltage applied to bit lines based on the current program loop number and the group to which memory cells belong. The control logic changes voltage conditions between odd and even program loops, creating a dynamic programming scheme that adapts to the progressive state of memory cell programming across multiple loops
2Manufacturing precision
If the number of program loops is increased to achieve better threshold voltage distribution, then programming precision improves, but RC delay increases and program performance deteriorates
Solution Approach 1:
The patent implements a periodic voltage application pattern where different voltage conditions are applied alternately in odd and even program loops. This periodic action creates a rhythm of programming that systematically addresses threshold voltage distribution across multiple loops while preventing excessive RC delay accumulation by varying the voltage conditions periodically
3Reliability
If program inhibit voltage is applied to all bit lines throughout the program operation, then memory cell performance is maintained, but the threshold voltage distribution cannot be optimized for different program loops
Solution Approach 1:
The patent applies different voltage qualities to different groups of memory cells based on their program loop characteristics. The first group of memory cells receives different voltage conditions than the second group, allowing each group to be optimized for its specific programming pattern and loop count, thereby achieving both performance maintenance and threshold voltage optimization
Data Source
AI summary
A semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes memory cells. The peripheral circuit performs a program operation including program loops on selected memory cells. The control logic controls the peripheral circuit to apply a program inhibit voltage to bit lines connected to memory cells of a first group of target states, apply the program inhibit voltage to bit lines connected to memory cells on which programming is determined to be completed in a previous program loop, among memory cells of a second group of target states, and apply a program allowable voltage to bit lines connected to memory cells on which programming is determined to not be completed in the previous program loop, among the memory cells of the second group of target states. The first and second groups are determined by a number of current program loops.