Memory Device Built-In Self-Test Controller for Wafer Level Testing
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Solution Overview
Problem
Conventional memory devices lack an efficient built-in self-test (BIST) capability, leading to costly and time-consuming testing processes, where a faulty memory device in a stack often results in discarding all devices in the package, limiting the ability to perform high-speed data path tests at the wafer level.
Innovation Solution
A memory device with a built-in self-test (BIST) controller that performs BIST write and read operations, generating pattern data and comparing it with sensed data to determine pass/fail signals, allowing for high-speed data path testing at the wafer level and reducing test costs and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing processes are used for memory devices, then testing can be performed, but the testing process is costly and time-consuming
Solution Approach 1:
The memory device performs self-testing through an integrated BIST controller that autonomously generates test patterns, executes write and read operations, and compares results without requiring external testing equipment. This self-service capability eliminates the need for costly and time-consuming external testing processes while maintaining high testing accuracy
Solution Approach 2:
The BIST controller generates test patterns and prepares test data in advance before actual testing begins. By pre-generating pattern data and organizing test sequences beforehand, the system enables rapid execution of comprehensive tests, significantly reducing the overall testing time while ensuring thorough coverage
2Reliability
If conventional testing processes are used for memory devices, then testing can be performed, but it is costly
Solution Approach 1:
By integrating the BIST controller directly into the memory device, the system eliminates the need for expensive external testing equipment and manual testing processes. The self-testing capability performs comprehensive reliability checks using only the device's own resources, dramatically reducing testing costs while maintaining high accuracy
Solution Approach 2:
The BIST controller creates internal copies of test patterns and reference data that can be repeatedly used for multiple test iterations. By generating and reusing these pattern copies within the device, the system avoids the need for expensive external test pattern generation and multiple physical test setups
3Reliability
If a faulty memory device is detected in a stack, then quality control is maintained, but all devices in the package must be discarded
Solution Approach 1:
The BIST controller enables independent testing of each memory device within a package, allowing quality assessment at the individual device level rather than treating the entire package as a single unit. This segmentation capability identifies and isolates only the faulty device, permitting discarding of the specific defective unit while retaining functional devices in the same package
Solution Approach 2:
The patent replaces the mechanical/package-level testing approach with an electronic/device-level BIST system. By substituting external package testing with internal device self-testing, the system achieves precise fault localization to the individual device level, eliminating the need for conservative package-wide rejection policies
4Productivity
If BIST operations are implemented in memory devices, then high-speed data path testing is enabled, but device complexity increases
Solution Approach 1:
The BIST controller is designed to perform multiple testing functions including pattern generation, write operations, read operations, and data comparison using a single integrated circuit. This multi-functional approach enables high-speed comprehensive testing without proportionally increasing device complexity, as one controller handles all test operations rather than requiring separate dedicated circuits for each function
Solution Approach 2:
The patent combines the BIST controller, pattern generator, and comparison logic into an integrated unit that shares resources with the memory device's existing data path. By merging the testing functions with the operational infrastructure, the system achieves high-speed testing capability while minimizing additional complexity through shared components and circuits
Data Source
AI summary
A memory device that supports a built-in self-test (BIST) operation includes: a plurality of memory cells; a page buffer group including page buffer circuits respectively coupled to the plurality of memory cells through bit lines; a built-in self-test (BIST) controller configured to generate pattern data to be stored in the page buffer circuits and reference data to be compared with sensed data obtained from the page buffer circuits, and to compare the reference data with the sensed data; and an input/output control circuit configured to input the pattern data to the page buffer circuits and to transfer the sensed data from the page buffer circuits to the BIST controller.