Memory Receiver Circuit DC Voltage Shift
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Solution Overview
Problem
Memory receivers in memory controllers face challenges in accurately reading data signals from memories with varying DC average voltage levels due to differences in memory protocols, configurations, and manufacturers, leading to inefficiencies and potential electrical overstress.
Innovation Solution
A memory receiver circuit with a differential amplifier that shifts the data signal to a constant DC average voltage level, independent of the input voltage, using a bias circuit to generate bias voltages and a voltage drop block to manage voltage levels, and a voltage offset compensation circuit to adjust for internal and rank-specific offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the reference voltage is set at the average DC voltage level of the data signal, then the data reading accuracy is improved, but the system cannot accommodate memories with different DC voltage levels from different protocols, manufacturers, or configurations
Solution Approach 1:
The patent implements a dynamic reference voltage adjustment mechanism where the reference voltage is automatically calibrated based on the actual data signal characteristics. The system includes a reference voltage generation circuit that can adapt its output level according to the specific memory device being accessed, allowing the same receiver to work optimally with different memory types (DDR3, DDR4, LPDDR, etc.) while maintaining high reading accuracy for each.
Solution Approach 2:
The system changes the reference voltage parameter dynamically based on memory device identification. During initialization, the receiver detects the memory type and configuration, then adjusts the reference voltage level accordingly. This parameter adaptation enables the system to achieve optimal measurement precision for each specific memory configuration without requiring hardware changes.
2Measurement precision
If the receiver circuit is designed to work with a specific memory protocol and voltage level, then the reading accuracy for that protocol is optimized, but the system requires multiple receiver circuits for different memory types
Solution Approach 1:
The patent designs a universal receiver circuit that can handle multiple memory protocols (DDR3, DDR4, LPDDR, etc.) through software-controlled parameter adjustment. The receiver includes a configurable reference voltage generation unit and adjustable amplification stages that can be programmed via registers to match different memory specifications. This single multi-functional receiver replaces what would traditionally require multiple dedicated receivers, reducing device complexity while maintaining optimized performance for each protocol.
3Measurement precision
If the reference voltage varies with memory characteristics, then each memory type can be read accurately, but the system switching between memory ranks takes longer due to voltage reconfiguration
Solution Approach 1:
The system performs preliminary characterization of different memory ranks during initialization or training phases. The optimal reference voltage levels and receiver parameters for each memory rank are pre-determined and stored in lookup tables or configuration registers. When switching between memory ranks, the system simply retrieves and applies the pre-configured parameters rather than performing full recalibration, significantly reducing the switching time while maintaining accurate reading performance for each rank.
4Adaptability or versatility
If the data signal voltage level is allowed to vary with memory configuration, then different memory types can be supported, but the receiver circuit may experience electrical overstress
Solution Approach 1:
The receiver circuit incorporates built-in protection mechanisms that are activated before potential overstress conditions occur. These include clamping diodes, voltage-limiting resistors, and configurable gain stages that prevent the input signal from exceeding safe voltage levels. The system also includes automatic detection of signal voltage levels and dynamic adjustment of receiver sensitivity to ensure that even high-voltage signals from certain memory configurations are safely conditioned before processing, preventing electrical damage while maintaining compatibility with diverse memory types.
Data Source
AI summary
Embodiments include systems, methods, and apparatuses for reading a data signal from a memory, such as a dynamic random access memory (DRAM). In one embodiment, a memory receiver may include a differential amplifier to receive a data signal from the memory and pass a differential output signal based on a voltage difference between the data signal and a reference voltage. The data signal may have a first direct current (DC) average voltage level, and the differential amplifier may shift the differential output signal to a second DC average voltage level that is substantially constant over a range of values of the first DC average voltage level. In another embodiment, a voltage offset compensation (VOC) circuit may apply a compensation voltage to the output signal that is based on an activated rank or an identity of the memory module. Other embodiments may be described and claimed.