Memory Circuit Leakage Compensation via Source Line Biasing
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Solution Overview
Problem
Shrinking semiconductor feature sizes lead to increased leakage current in unselected memory cells, affecting the correct sensing of selected memory cells and compromising the operation of both nonvolatile and volatile memory systems, particularly in high-density memory applications like Flash EEPROM and SRAM.
Innovation Solution
The implementation of a memory array with a word line and bit line, where a bias circuit applies a supply voltage to the second terminals of memory cells in one mode and a different bias voltage in another mode, utilizing source line bias circuits to reduce leakage current by raising the source line voltage of unselected memory cells on a selected bit line, thereby minimizing leakage current and improving signal-to-noise ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes of high density memory cells are reduced to increase storage capacity, then memory density is improved, but leakage current in unselected memory cells increases
Solution Approach 1:
The patent applies different voltage levels to different groups of memory cells based on their selection state. Specifically, unselected memory cells on the selected bit line are maintained at a different voltage (VSSL) compared to selected memory cells, creating localized voltage differentiation that suppresses leakage current in unselected cells while maintaining proper operation of selected cells
Solution Approach 2:
The patent dynamically changes the voltage parameter of memory cells based on their selection state. By switching between VSSL and VSS levels on source lines, the patent modifies the electrical parameters of memory cells to minimize leakage current in unselected cells during read operations, directly addressing the leakage problem caused by feature size reduction
2Quantity of substance
If leakage current in unselected memory cells increases due to smaller feature sizes, then sensing accuracy of selected memory cells deteriorates, but reducing feature sizes improves memory capacity
Solution Approach 1:
The patent creates localized voltage conditions on the bit line by maintaining unselected memory cells at a different voltage state. This local voltage differentiation ensures that only the selected memory cell contributes significantly to the bit line current, improving sensing accuracy by suppressing leakage contributions from unselected cells
Solution Approach 2:
The patent preemptively applies voltage biasing to unselected memory cells before the sensing operation to prevent leakage current from affecting the measurement. By establishing the voltage differential in advance through source line control, the patent prevents leakage interference before it can degrade sensing accuracy
3Ease of operation
If supply voltage is applied to all memory cells during operation, then memory cell operation is simplified, but leakage current in unselected memory cells increases
Solution Approach 1:
The patent divides the memory array into multiple segments with independent source line control. Each source line can be independently biased to different voltage levels (VSSL or VSS), allowing selective voltage application to different groups of memory cells. This segmentation enables differential voltage schemes that reduce leakage while maintaining operational simplicity through standardized cell designs
Solution Approach 2:
The patent makes the source line bias circuit multi-functional by enabling it to serve both as a voltage supply during read operations and as a leakage suppression mechanism. The same source line infrastructure that provides necessary voltage during normal operation is also used to apply differential biasing to unselected cells, eliminating the need for separate leakage control circuitry
Data Source
AI summary
A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.