3D In-Memory Computing Circuit for Parallel AI Processing
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Solution Overview
Problem
Current in-memory computing architectures face limitations due to power consumption, timing penalties, and heat dissipation in multi-stacked die structures, which hinder efficient data communication and computation speed in AI applications.
Innovation Solution
A 3D chip integration approach with vertically stacked memory dies and conductive pillars is employed, enabling parallel and pipeline computing operations, utilizing memory arrays with access transistors and storage capacitors, and incorporating a memory controller for efficient data management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory dies are stacked vertically to increase memory capacity and enable parallel computing operations, then computation efficiency and memory bandwidth are improved, but power consumption and heat dissipation increase due to chip-to-chip communication
Solution Approach 1:
The patent transitions from 2D planar memory architecture to 3D vertically stacked architecture, enabling multiple memory dies to be stacked along the vertical dimension. This allows parallel computing operations across multiple layers while increasing memory capacity without proportionally increasing power consumption, as the vertical stacking reduces the communication distance compared to expanding in 2D plane.
Solution Approach 2:
The patent divides the computing system into multiple independent memory dies stacked vertically, where each die can perform computing operations independently and in parallel. This segmentation enables distributed computing across layers, improving overall computation efficiency while managing power consumption through localized operations rather than centralized processing.
2Speed
If multiple memory dies are stacked vertically to enable parallel MAC operations, then computation speed is improved, but timing penalty increases due to chip-to-chip communication
Solution Approach 1:
By stacking memory dies vertically in the third dimension, the patent enables simultaneous MAC operations across multiple layers, effectively increasing computation speed through parallel processing. The vertical architecture allows data to be processed in parallel across different height levels, reducing the timing penalty associated with sequential processing in 2D architectures.
Solution Approach 2:
The patent combines multiple memory dies into a single integrated 3D stack, allowing them to function as one unified computing unit. This merging enables coordinated parallel operations where multiple dies work together on different aspects of the same computational task, improving overall computation speed while managing communication overhead through integrated control.
3Quantity of substance
If multiple memory dies are stacked vertically to increase memory capacity, then memory bandwidth is improved, but device complexity increases
Solution Approach 1:
The patent increases memory capacity by stacking dies vertically rather than expanding horizontally, which would require proportionally more interconnect structures and control logic. The vertical stacking approach achieves higher capacity with more manageable complexity by utilizing the third dimension for capacity expansion while keeping the footprint and interconnect complexity relatively controlled.
Data Source
AI summary
An in-memory computing circuit is provided. The in-memory computing circuit includes a core die, a plurality of conductive pillars, and a plurality of memory dies. The plurality of memory dies are coupled to the core die through the plurality of conductive pillars and are configured to implement computing operation. The plurality of memory dies includes at least one of the memory dies disposed on a bottommost memory die of the plurality of memory dies. The plurality of memory dies receives an input data from the core die through a common input terminal of the core die.