3D Memory Device Fabrication via Vertical Stacking and Alignment Marks
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and struggle with inter-chip interconnects that dominate IC performance and power consumption.
Innovation Solution
The development of a method for producing 3D memory devices using a multilayer structure with single crystal layers, alignment marks, and Through-Silicon Via (TSV) technology, allowing for the construction of configurable logic, memory, and I/O dies with reduced interconnect size and increased connectivity, enabling efficient 3D IC technology for various applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional 2D semiconductor fabrication methods are used, then manufacturing processes are well-established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent transitions from conventional 2D planar fabrication to 3D vertical stacking by forming multiple levels (first level, second level, third level) stacked vertically. This dimensional change enables higher density interconnects and reduces the need for extensive lateral routing, thereby reducing mask-set requirements while maintaining manufacturing feasibility through established etching and deposition processes adapted for vertical architectures.
Solution Approach 2:
The invention divides the semiconductor device into multiple discrete levels or layers, each containing specific circuit elements (memory cells, interconnects, alignment marks). This segmentation allows independent fabrication and optimization of each level, enabling greater product flexibility and reducing the complexity of single-plane mask sets while maintaining ease of manufacture through modular processing.
2Adaptability or versatility
If more mask sets are used to achieve product diversity, then adaptability increases, but manufacturing costs increase
Solution Approach 1:
The patent implements universal alignment marks that serve multiple functions: they enable alignment across different levels (first, second, third levels), support various lithography steps, and facilitate precise positioning of diverse circuit elements. This multi-functionality reduces the need for separate alignment systems for different products, thereby increasing adaptability while reducing overall mask-set requirements and manufacturing costs.
Solution Approach 2:
By moving to 3D vertical stacking with multiple levels, the patent reduces lateral routing requirements and enables higher density interconnects. This dimensional change allows a single set of lithography masks to define structures across multiple vertical levels, reducing the total number of mask sets needed while achieving greater product diversity through vertical integration.
3Ease of operation
If inter-chip interconnects are used to achieve connectivity, then device functionality is enabled, but IC performance and power consumption are dominated by interconnect limitations
Solution Approach 1:
The patent merges multiple functional levels (memory cells, interconnects, control circuits) into a single integrated 3D structure where first, second, and third levels are vertically stacked and electrically connected through through-silicon vias (TSVs). This consolidation eliminates the need for separate inter-chip interconnects, thereby improving IC performance and reducing power consumption while maintaining full device functionality.
Solution Approach 2:
The invention transitions from lateral inter-chip interconnects to vertical within-chip interconnects by stacking multiple levels vertically. This dimensional change shortens interconnect lengths, increases bandwidth, and reduces power consumption while enabling full device functionality through efficient vertical routing and TSV technology.
Data Source
AI summary
A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits including first single crystal transistors; forming at least one second level above the first level; performing a first etch step including etching first holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching second holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where the etching first holes includes performing a lithography step aligned to the first alignment marks.