Transistor TRIZ Cases

Replacing silicon nitride spacers with low-k dielectrics after silicidation reduces parasitic capacitance and circuit delay.

Germanium oxide supporting patterns prevent bowing and tilting during etching to maintain uniform through hole widths.

Vertical stacking of IC and power MOSFET chips reduces on-resistance through common drain electrodes while minimizing package volume.

A method corrects exposure mask distortion using test patterns and illumination systems to improve alignment accuracy.

A monocrystal chip integrates enhancement-mode MOSFETs and a depletion-mode JFET for precise current sensing and reliable high-voltage startup.

A dual capping layer approach applies tensile stress to NMOS and compressive stress to PMOS source drain regions during re-crystallization.

A gate driver circuit sets an intermediate voltage level to turn on field-effect transistors during normal power conditions.

Direct contact formation over active gates reduces wasted isolation area, increasing device integration density.

Alternating rows of logic cells with discontinuous and continuous active regions balance processing power against chip area constraints.

Directly connecting pseudo bumps forms redistribution interconnects, reducing resistance and inductance while eliminating costly plating steps.

Integrating an HJFET with an HBT creates a lambda diode that generates negative differential resistance without requiring high transistor gain.

An oxide semiconductor transistor reduces leakage current to retain data indefinitely, eliminating the need for refresh operations and high voltage.

Implanting non-dopant ions into trench sidewalls modifies the isolation region to control active area electrostatics.

A control circuit applies a pre-bias potential to the gate of a power transistor before body diode conduction begins.

Cross-coupling a floating diffusion node to an adjacent reset transistor prevents gate interference and maintains signal-to-noise ratio without altering layout.

A vertical memory device uses sub-interconnections to link selection lines and bit lines across stacked pillars.

A metal-insulator-metal capacitor sits under an inductor coil to shrink the footprint of radio-frequency integrated circuits.

A semiconductor device structure uses a stress absorbing layer filling dielectric trenches to distribute mechanical loads across flexible substrates.

A vertical channel non-volatile memory cell uses nested gates to reduce footprint area.

Continuous spacers extend integrally across gate stacks and dummy gates to self-align fin ends with spacer inner walls.

Graded impurity regions reduce electric field strength at pn junctions, suppressing dark current and thermal noise in laminated imaging devices.

Counter-doped well structure neutralizes out-diffused dopants to stabilize bipolar junction transistor electrical characteristics.

An insulating layer within transistor recesses blocks impurity diffusion into the channel while preserving high doping levels for improved drive current.

Dilute hydrofluoric acid etches the oxide semiconductor film to reduce thickness, preventing gate insulating film disconnection during electrode formation.

Replacing physical fin active region barriers with electrical control reduces characteristic variations while maintaining compact integrated circuit designs.

Self-aligned spacer sidewalls prevent source dopant penetration, controlling lateral diffusion and protecting floating gate tip sharpness.

A BJT pixel circuit boosts an adjustable ground level to prevent storage capacitor voltage saturation.

A display array substrate uses a gate dielectric layer with varying thickness regions to control electric fields and reduce parasitic capacitance.

A BCE-type thin film transistor uses a dual-layer SiOx passivation structure to protect the oxide semiconductor layer during fabrication.

A composite organic semiconductor film combines a specific compound with a binder polymer to achieve high charge mobility.

A current sense circuit uses a variable retarder to delay comparison signals proportionally to the square of an initial time interval.

Nested apertures reduce drain electrode area to resolve space constraints, enabling high pixel density manufacturing.

Resist masking prevents etching residues at step portions between fins and isolation regions, ensuring device reliability.

A 3D memory device fabrication method uses vertical stacking with single crystal layers and alignment marks to enable precise lithography across multiple levels.

Segmented conductive straps with increased spacing prevent breakdown during write operations.

A non-volatile memory device uses a high resistance region to generate a strong electric field for carrier injection.

Vertical vias connect interdigitated anode and cathode lines to increase capacitance density while a shield structure reduces energy loss.

Alternating trench profiles reduce capacitive coupling while maintaining high line density.

Merging the gate and source terminals into a single common structure reduces the memory area and fabrication costs of conventional single-gate devices.

An RC-based NMOS power clamp uses an external resistor to create parallel discharge paths for electrostatic discharge protection.

Vertical stacking shares channels and interconnects, cutting SRAM area by 40% while easing fabrication complexity.

Alternating segmented dummy contacts and gates with isolation gaps prevent electrical shorts from enlarged holes in high-density SRAM arrays.

A semiconductor layout structure uses an asymmetrical channel region to deflect concentrated electric fields and reduce leakage current.

Heat-induced polymer contraction creates scalable, spatially selective crumples in two-dimensional materials while preserving material integrity.

A thin film transistor uses a planar layout where the gate electrode and semiconductor portion projections do not overlap on the substrate.

A piezoelectric integrated thin film transistor couples with micro-electrical-mechanical systems to transmit and receive ultrasonic pressure waves.

Segmented In-Ga-Zn-O oxide layers reduce channel defects and contamination while maintaining high electrical reliability.

Bias conducting wires couple parasitic transistor bases to ensure uniform ESD current bypass without increasing layout area.

Inactive fins with reduced conductivity minimize junction leakage in vertical FinFET arrays, resolving dimensional uniformity challenges at array edges.

High-pressure plasma nitridation enhances nitrogen selectivity in silicon regions while minimizing oxide oxidation for reliable NAND flash memory.