Pillar-Shaped Semiconductor Active Patterns for High Integration
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Solution Overview
Problem
The increasing demand for high integration and high-speed semiconductor devices poses challenges in manufacturing, particularly due to reduced process margins in photolithography and the need for advanced patterning techniques.
Innovation Solution
The development of semiconductor devices with pillar-shaped active patterns, fully doped with dopants of a single conductivity type, and the integration of gate electrodes, insulating layers, bit lines, and capacitors, which eliminates the need for p-type/n-type junctions, allowing for efficient channel region operation without junction-induced leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography is used for patterning, then manufacturing process is simple, but process margin is reduced and fine pattern definition becomes difficult
Solution Approach 1:
The patterning process is divided into multiple steps: first forming mandrels with initial photolithography, then using these mandrels as templates for depositing sacrificial materials, and finally forming the final active patterns through selective removal. This segmentation allows each step to be optimized independently, achieving fine pattern definition while managing process complexity.
Solution Approach 2:
Mandrels are formed in advance before the actual active patterns are created. These preliminary structures serve as templates that guide the subsequent deposition and patterning steps, enabling precise pattern transfer while simplifying the overall process by pre-establishing the geometric framework.
2Reliability
If p-type/n-type junctions are used in active patterns, then conventional transistor operation is achieved, but junction-induced leakage occurs and performance is reduced
Solution Approach 1:
The invention extracts and removes the p-n junction structures from the active pattern. By using fully doped regions of a single conductivity type instead of junction-based transistors, the harmful leakage effects are eliminated while transistor operation is maintained through alternative mechanisms such as surface channel formation or depletion mode operation.
Solution Approach 2:
The conductivity type parameter is changed from requiring both p-type and n-type regions to using only a single conductivity type throughout the active pattern. This parameter change fundamentally alters the transistor operation mechanism, eliminating junction-induced leakage while maintaining device functionality through modified conduction paths.
3Quantity of substance
If active patterns are made smaller for high integration, then device density increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patterning process uses nested structures where mandrels are embedded within sacrificial material layers, which in turn are surrounded by the final active pattern materials. This nested approach allows multiple pattern layers to be formed using the same underlying template, achieving high density while maintaining precision through repeated use of the same high-precision mandrel structures.
Solution Approach 2:
The mandrel patterns serve as master templates that are copied multiple times through successive deposition and transfer steps. By copying the same high-precision mandrel pattern rather than directly patterning each active region, the manufacturing precision is preserved while enabling high integration through multiple copied instances.
Data Source
AI summary
A method of manufacturing a semiconductor device may include: forming active patterns of pillar-shapes upward protruding from a substrate, the active patterns fully doped with dopants of one conductivity type; forming a gate electrode extending in one direction, the gate electrode overlapped with sidewalls of the active patterns; and forming a gate insulating layer between the gate electrode and the active patterns.