U-Shaped SONOS Memory With Elevated Source and Drain
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Solution Overview
Problem
Flash memory with a SONOS structure faces challenges in miniaturization due to increased bit line resistance and reduced channel length, making it difficult to separate charge storage regions and maintain threshold voltage.
Innovation Solution
A semiconductor device with bit lines formed from epitaxial semiconductor layers on a substrate, where the charge storage layer is positioned between these layers, allowing for reduced channel length and miniaturization of memory cells by defining bit line width through epitaxial layer width, and optionally forming a groove for the charge storage layer to stabilize channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the implantation dose amount is increased to lower the bit line resistance, then the bit line resistance is reduced, but the dopant diffuses in lateral and longitudinal directions to reduce the channel length
Solution Approach 1:
The bit line is repositioned from inside the semiconductor substrate to the surface, forming an elevated structure. This dimensional change allows the bit line to be separated from the channel formation region, enabling independent control of bit line doping without affecting channel length. The elevated bit line is formed by implanting dopants into the semiconductor substrate at a position separated from the channel region in the depth direction.
Solution Approach 2:
The doping process is segmented into separate regions: the bit line region receives high-dose implantation for low resistance, while the channel region maintains appropriate doping levels. This segmentation is achieved by forming the elevated bit line structure that is spatially separated from the channel, allowing independent dopant diffusion control in each region.
2Productivity
If the memory cell is miniaturized to increase integration density, then the integration density is improved, but the channel length is reduced making it difficult to separate charge storage regions
Solution Approach 1:
The bit line is elevated to the surface and separated from the channel region in the depth direction. This vertical separation allows the channel length to be maintained at appropriate lengths for charge storage region separation, while the overall cell area is reduced through the elevated structure, enabling miniaturization without compromising channel length requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the miniaturization of memory cells while maintaining channel length, reducing bit line resistance, and allowing independent control of impurity densities to prevent threshold voltage lowering.
Implementation Method 1
bit lines formed of a semiconductor epitaxially grown
Implementation Method 2
a transistor which operates as a memory cell and includes a floating gate or an insulating film called a charge storage layer for accumulating electrons used to store data
Implementation Method 3
the implantation dose amount is required to be increased for lowering the resistance of the bit line. However, if the implantation dose amount is increased, the dopant diffuses both in the lateral and longitudinal directions
Data Source
AI summary
A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes two epitaxial semiconductor layers formed on a semiconductor substrate, bit lines formed on upper portions of the two epitaxial semiconductor layers, and a charge storage layer formed on the semiconductor substrate between the two epitaxial semiconductor layers.