Vertical Memory Device Pillar Sub-Interconnections
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Solution Overview
Problem
The integration density of traditional two-dimensional (2D) or planar memory devices is limited by the cost and complexity of fine pattern technology, which restricts the increase in memory cell density and performance.
Innovation Solution
A vertical-type memory device is designed with vertically arranged pillars and sub-interconnections that connect selection lines and bit lines, allowing for a more compact and efficient memory cell structure, increasing integration density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar memory device structure is used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertical structure by stacking multiple selection lines (first, second, and third selection lines) and their corresponding vertical pillars in the vertical direction. This dimensional change allows multiple memory cells to be stacked above each other, significantly increasing integration density without requiring finer lateral patterning, thus maintaining manufacturing simplicity while achieving higher density.
2Quantity of substance
If fine pattern technology is used to increase integration density, then memory cell density increases, but manufacturing cost and complexity increase
Solution Approach 1:
Instead of increasing lateral pattern fineness, the patent stacks memory cells vertically by creating multiple selection lines and vertical pillars at different heights. This approach achieves higher memory cell density by utilizing the vertical dimension rather than pushing the limits of lateral photolithography resolution, thereby avoiding the need for expensive and complex fine pattern technology.
Solution Approach 2:
The patent implements a nested structure where multiple selection lines and their corresponding vertical pillars are stacked one above another in the vertical direction. Each selection line and pillar pair is nested within the same lateral footprint area, allowing multiple memory cells to occupy the same planar space at different vertical levels, thus increasing density without increasing lateral complexity.
3Quantity of substance
If vertical-type memory device structure is used, then integration density increases, but device structure complexity increases
Solution Approach 1:
The patent achieves higher integration density by stacking selection lines and vertical pillars vertically, creating a three-dimensional structure. While this increases structural complexity compared to planar devices, the vertical stacking allows multiple memory cells to share the same lateral footprint, and the sub-interconnections provide a systematic way to route signals between stacked cells, making the complexity manageable.
Solution Approach 2:
The patent divides the memory device into multiple stacked segments, each consisting of a selection line, vertical pillars, and associated memory cells. The sub-interconnections further segment the routing paths, allowing independent access to different vertical levels. This segmentation modularizes the complex three-dimensional structure, making it easier to manufacture and control despite the increased density.
4Speed
If sub-interconnections are added to connect vertical pillars across selection lines, then read/write speed improves, but device complexity increases
Solution Approach 1:
The patent introduces sub-interconnections as intermediary structures that bridge vertical pillars associated with different selection lines. These sub-interconnections act as mediators, enabling direct data transfer between memory cells on different vertical levels without requiring data to traverse through bit lines and word lines multiple times. This intermediary pathway accelerates read/write operations by providing shortcut connections, justifying the increased interconnection complexity.
Data Source
AI summary
Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.