Single Gate-Source Common Terminal Non-Volatile Memory
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Solution Overview
Problem
Conventional single-gate non-volatile memories have a larger area and higher fabrication costs due to independent gate, source, and drain voltages, making them less cost-effective.
Innovation Solution
A non-volatile memory with a single gate-source common terminal is proposed, where the source and single floating gate are connected to share a common bias, reducing the number of control lines and fabrication costs by using a semiconductor substrate with ion-doped regions and capacitor structures to form a three- or four-terminal structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If independent gate, source, and drain voltages are used in conventional single-gate non-volatile memory, then the memory can perform basic storage functions, but the area increases and fabrication cost increases
Solution Approach 1:
The gate and source terminals are merged into a single common terminal structure. The first electric-conduction gate and second electric-conduction gate are mechanically separated but electrically connected, forming a unified control structure that eliminates the need for separate gate and source control lines, thereby reducing area while maintaining storage functionality
Solution Approach 2:
The single gate-source common terminal serves multiple functions: it acts as both the gate control terminal and the source terminal for the transistor. This multi-functional terminal structure eliminates redundant control lines and reduces the overall memory cell area while preserving all necessary storage operations
2Reliability
If independent gate, source, and drain voltages are used in conventional single-gate non-volatile memory, then the memory can perform basic storage functions, but the fabrication cost increases
Solution Approach 1:
By merging the gate and source terminals into a single common terminal, the number of required control lines and interconnect structures is reduced. This simplification directly lowers fabrication complexity and cost while maintaining the essential storage function through the unified terminal structure
Solution Approach 2:
The invention extracts and eliminates the redundant separate gate terminal from the conventional structure. By removing the independent gate terminal and its associated control line, fabrication steps are simplified and costs are reduced, while the gate function is integrated into the common gate-source terminal
3Reliability
If independent gate, source, and drain voltages are used in conventional single-gate non-volatile memory, then the memory can perform basic storage functions, but the number of control lines increases
Solution Approach 1:
The gate and source control functions are merged into a single common terminal, eliminating the need for separate control lines. This reduction in control line complexity directly improves device layout simplicity while maintaining full storage functionality through the integrated terminal structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces the area and fabrication costs of single-gate non-volatile memories while maintaining functionality, enhancing product value by eliminating the need for independent control gate lines.
Implementation Method 1
A non-volatile memory is programmed via keeping charges to vary the gate voltage of the transistor thereof
Implementation Method 2
The transistor includes a first electric-conduction gate stacked on the first dielectric layer
Data Source
AI summary
A non-volatile memory with a single gate-source common terminal and an operation method thereof are provided. The non-volatile memory includes a transistor and a capacitor structure both embedded in a semiconductor substrate. The transistor includes a first dielectric layer, a first electric-conduction gate and several first ion-doped regions. The capacitor structure includes a second dielectric layer, a second electric-conduction gate and a second ion-doped region. The memory may further include a third ion-doped region below the second dielectric layer. The first and second electric-conduction gates are electrically connected to form a single floating gate of the memory cell. The source and second ion-doped region are electrically connected to form a single gate-source common terminal.