ESD Protection Device Using Bias Conducting Wire for Uniform Current Bypass
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Solution Overview
Problem
Conventional ESD protection circuits face non-uniform ESD current bypassing issues due to varying base resistances of parasitic transistors, leading to weakened protection ability and increased layout complexity, especially in deep-submicron CMOS processes.
Innovation Solution
The ESD protection device employs a bias conducting wire to couple the bases of parasitic transistors together, ensuring simultaneous triggering of ESD protection units under high voltage, and incorporates a multi-finger layout to reduce silicon area while maintaining effective ESD current bypassing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a multi-finger layout is used to reduce occupied silicon area, then the layout area is reduced, but the base resistance of parasitic transistors becomes non-uniform
Solution Approach 1:
The patent applies equipotentiality by connecting the substrate contacts of all parasitic transistors to a common substrate potential through a shared substrate contact region. This ensures that despite the multi-finger layout geometry, all parasitic transistors experience the same substrate potential, thereby achieving uniform base resistance across all fingers while maintaining compact layout area.
2Device complexity
If the base resistances of parasitic transistors are made non-uniform, then the layout complexity is reduced, but the ESD current bypassing becomes non-uniform
Solution Approach 1:
The patent merges the substrate contacts of all parasitic transistors into a single shared substrate contact region. This combining approach maintains uniform base resistance across all parasitic transistors, ensuring that ESD current is distributed uniformly among all fingers during breakdown, thereby improving ESD protection reliability while keeping the layout relatively simple.
3Reliability
If a large channel width is used to withstand high voltage ESD, then the ESD protection ability is improved, but the occupied silicon area increases
Solution Approach 1:
The patent segments the total channel width into multiple parallel fingers, each with a smaller individual width. The sum of all finger widths provides the total ESD protection capability, while the segmented structure reduces the occupied silicon area compared to a single large-width transistor. Each finger acts as an independent ESD protection unit with its own parasitic transistor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables timely and uniform bypassing of ESD current, enhancing the ESD protection ability and maintaining performance under mixed-voltage operations without increasing layout area.
Implementation Method 1
employ a bias conducting wire to couple the bases of parasitic transistors together, ensuring simultaneous triggering of ESD protection units under high voltage
Implementation Method 2
When the high voltage 205 exceeds a drain/substrate breakdown voltage of the NMOS transistor, the drain/substrate of the NMOS transistor may be broken down and generate a bulk current which triggers parasitic transistors inside the NMOS transistor to bypass the ESD current
Data Source
AI summary
An electrostatic discharge (ESD) protection device and a layout thereof are provided. A bias conducting wire is mainly used to couple each base of a plurality of parasitic transistors inside ESD elements together, in order to simultaneously trigger all the parasitic transistors to bypass the ESD current, avoid the elements of a core circuit being damaged, and solve the non-uniform problem of bypassing the ESD current when ESD occurs. Furthermore, in the ESD protection layout, it only needs to add another doped region on a substrate neighboring to, but not contacting, doped regions of the ESD protection elements and use contacts to connect the added doped region, so as to couple each base of the parasitic transistors together without requiring for additional layout area.