3D Select Gate Electrodes for Nonvolatile Memory Chip Size Reduction
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Solution Overview
Problem
Conventional nonvolatile memory devices face challenges with increased chip size due to wider select lines, complex fabrication processes, and difficulties in design rule adherence, particularly with hot carrier injection and charge blocking layer removal.
Innovation Solution
The solution involves forming select gate electrodes over a cell string with a gate dielectric layer interposed between the channel layers, simplifying the fabrication process and improving operation characteristics by reducing chip size and preventing hot carrier injection perturbations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If select lines are made wider to occupy larger area, then select line width increases, but chip size increases
Solution Approach 1:
The patent transitions from planar select lines to three-dimensional select gate electrodes that wrap around channel layers in a vertical dimension. This allows the select gate to control the channel from multiple directions (surrounding it), achieving better control without increasing the lateral chip area. The select gate electrode extends along the channel length and wraps around the channel layer, utilizing the vertical stacking dimension to provide comprehensive control.
2Length of moving object
If separate processes are used to form select lines with different width from word lines, then select line width differentiation is achieved, but fabrication process complexity increases
Solution Approach 1:
The patent merges the formation of select gate electrodes with the existing word line fabrication process. Both are formed as stacked structures using the same spacer patterning technique. The select gate electrode and word line are created in an integrated manner through conformal deposition and etching processes, eliminating the need for separate selective width adjustment processes.
Solution Approach 2:
The spacer patterning process is made universal to form both word lines and select gate electrodes. The same deposition and etching sequences are used for both structures, with the select gate electrode forming part of the multi-layered gate stack that includes tunnel dielectric, charge trapping layer, blocking dielectric, and control gate, all formed through integrated processes.
3Area of stationary object
If word lines adjoin select lines, then layout density increases, but hot carrier injection perturbation occurs
Solution Approach 1:
The patent introduces a charge blocking layer as an intermediary between the control gate (select line) and the channel layer. This blocking dielectric layer prevents hot carriers generated in the control gate from injecting into the channel and causing perturbation. The charge blocking layer acts as a protective barrier that maintains electrical isolation while allowing the select gate to control the channel through electric field effects.
4Manufacturing precision
If design rule decreases, then device scaling is achieved, but charge blocking layer removal difficulty increases
Solution Approach 1:
The patent applies local quality by making the charge blocking layer selectively removable in specific regions. The charge blocking layer is retained in word line regions where it provides necessary electrical isolation, but is selectively removed in select gate regions where it would interfere with select gate functionality. This localized differentiation allows design rule scaling while maintaining manufacturability through selective etching processes.
Data Source
AI summary
A nonvolatile memory device includes cell strings, each including a plurality of memory cells over a substrate, extending in a direction, channel layers, connected with one sides and the other sides of the cell strings, extending in another direction perpendicular to the substrate, select gate electrodes, located over the cell strings, surrounding side surfaces of the channel layers with a gate dielectric layer interposed therebetween, and conductive lines connected with upper ends of the channel layers.