Split Gate Device Fabrication via Segmented Oxide Growth
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Solution Overview
Problem
The integration process for split gate devices with periphery devices on the same semiconductor chip often results in performance degradation due to exposure of periphery device gates to deposition and removal steps, leading to undesired process variations and narrowing of gate lengths.
Innovation Solution
A method for fabricating split gate devices and periphery devices where the gate oxide layer is grown before forming trench formations, and the charge trapping dielectric layer is formed after the gate oxide layer, ensuring that the periphery device gate is not exposed to the deposition and removal steps, thereby preventing performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If periphery device gates are exposed to deposition and removal steps during integration, then split gate device fabrication is enabled, but manufacturing precision and reliability of periphery devices deteriorate due to gate length narrowing and process variations
Solution Approach 1:
The substrate is divided into a core region for split gate devices and a periphery region for periphery devices. This spatial segmentation allows different fabrication processes to be applied to each region independently, enabling the periphery region to be protected from deposition and removal steps while the core region undergoes these steps for split gate formation.
Solution Approach 2:
Trench formations are formed in the periphery region before the deposition and removal steps are applied to the core region. This preliminary action ensures that the periphery device gates are already in place and protected, preventing any narrowing or damage during subsequent processing of the split gate devices.
2Ease of manufacture
If periphery device gates are exposed to deposition and removal steps, then split gate device fabrication is enabled, but device reliability deteriorates due to performance degradation
Solution Approach 1:
The substrate is divided into a core region for split gate devices and a periphery region for periphery devices. This spatial segmentation allows different fabrication processes to be applied to each region independently, enabling the periphery region to be protected from deposition and removal steps while the core region undergoes these steps for split gate formation.
Solution Approach 2:
Trench formations are formed in the periphery region before the deposition and removal steps are applied to the core region. This preliminary action ensures that the periphery device gates are already in place and protected, preventing any narrowing or damage during subsequent processing of the split gate devices.
3Manufacturing precision
If gate oxide layer is grown before trench formations, then periphery device gate protection is achieved, but process sequence complexity increases
Solution Approach 1:
The gate oxide layer is grown in the periphery region before the trench formations are created. This preliminary action establishes a protective layer that prevents subsequent deposition and removal steps from affecting the periphery device gates, ensuring their dimensions remain precise throughout the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents the narrowing of periphery device gates and reduces process variations, enhancing the performance and reliability of integrated split gate and periphery devices.
Implementation Method 1
the gate oxide layer is grown before forming trench formations
Implementation Method 2
the charge trapping dielectric layer is formed after the gate oxide layer
Data Source
AI summary
A split gate device that includes a memory gate and a select gate disposed side by side, a dielectric structure having a first portion disposed between the memory gate and a substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate, and a spacer formed over the select gate along an inner sidewall of the memory gate. Other embodiments of embedded split gate devices including high voltage and low voltage transistors are also disclosed.