FinFET Isolation via Sacrificial Spacer Patterning
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Solution Overview
Problem
The integration of semiconductor devices is limited due to the need for electrical isolation between fin-shaped FinFET devices, which requires additional space and reduces device density.
Innovation Solution
A method involving the formation of a patterned sacrificial layer with spacers on its sidewalls, allowing for a layout pattern transfer to the target layer, resulting in features with vertical and horizontal segments, where the spacing between adjacent vertical segments can be less than the minimum feature size achievable by current exposure apparatuses, thereby reducing the spacing between adjacent FinFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrical isolation structures are disposed between adjacent FinFET devices, then electrical isolation is achieved, but additional space is required which reduces device integration density
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary element that enables the formation of shared isolation structures. This sacrificial layer is temporarily placed between adjacent FinFET devices, allows for the creation of common isolation regions, and is subsequently removed. This mediator approach permits electrical isolation to be achieved while sharing the isolation structure between multiple devices, thereby reducing the total space required and improving device integration density.
2Manufacturing precision
If minimum feature size is constrained by exposure apparatus capabilities, then manufacturing precision is limited, but closer spacing between devices cannot be achieved
Solution Approach 1:
The patent applies preliminary action by first forming the sacrificial layer and using it as a template to define the positions of isolation structures before the actual device features are patterned. This preliminary structuring allows the subsequent patterning steps to achieve closer spacing than would be possible with direct exposure, effectively working around the minimum feature size constraints of the exposure apparatus.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning constraints to three-dimensional structure formation. By using the sacrificial layer to create vertical or multi-layer isolation structures, the design moves beyond the lateral resolution limits of the exposure apparatus, achieving closer effective spacing through vertical dimension utilization rather than being constrained by horizontal feature size limits.
Data Source
AI summary
A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of each of the sacrificial features, wherein all of the spacers are arranged to have a layout pattern; and transferring the layout pattern to the target layer so as to form a first feature and a second feature, wherein the first feature comprises a vertical segment and a horizontal segment, the second feature comprises a vertical segment and a horizontal segment, and a distance between the vertical segment of the first feature and the vertical segment of the second feature is less than a minimum feature size generated by an exposure apparatus.