Fin Electrostatic Barrier for Stacked Transistors
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Solution Overview
Problem
Conventional semiconductor technologies limit the formation of transistors to only the top portion of a fin, preventing the utilization of the bottom section for device formation, which restricts the integration of stacked devices on the same fin.
Innovation Solution
An electrostatic barrier layer is formed within the fin to create vertical isolation, allowing for the formation of transistors both above and below the barrier layer, enabling the integration of stacked devices on the same fin by patterning the barrier layer and appropriate doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are formed only on the top portion of a fin, then the manufacturing process is simple, but the device density is limited
Solution Approach 1:
The fin is divided into multiple sections by introducing an electrostatic barrier layer at a specific height, creating distinct top and bottom regions. This segmentation allows independent transistor formation on each section, effectively doubling the device density on the same fin structure without requiring completely new manufacturing processes.
Solution Approach 2:
The invention transitions from two-dimensional planar transistor arrangement to three-dimensional vertical stacking by utilizing the height dimension of the fin. Transistors are formed both above and below the electrostatic barrier layer, effectively using the vertical dimension to increase device density while maintaining compatibility with existing planar processing techniques.
2Adaptability or versatility
If the bottom section of the fin is not used for transistor formation, then the electrostatic control is simple, but the integration of stacked devices is restricted
Solution Approach 1:
An electrostatic barrier layer is introduced as an intermediary element within the fin structure. This barrier layer acts as a mediator that enables independent electrostatic control of transistors formed above and below it, allowing stacked device integration while maintaining manageable electrostatic control through the barrier's presence at a specific height.
Solution Approach 2:
The electrostatic barrier layer is positioned at a specific height within the fin, creating different electrostatic environments in the top and bottom sections. This local differentiation allows tailored electrostatic control for transistors in each region, enabling versatile device integration with controlled complexity.
3Productivity
If an electrostatic barrier layer is introduced to enable stacked transistors, then the device density increases, but the manufacturing process becomes more complex
Solution Approach 1:
The electrostatic barrier layer is formed within the fin structure before the transistor formation process. This preliminary action prepares the fin with pre-defined electrostatic zones, allowing subsequent transistor fabrication to proceed using standard processes while achieving enhanced device density through the pre-established vertical segmentation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of stacked transistors on both the top and bottom sections of a fin, facilitating the creation of interconnected devices, thereby enhancing device density and functionality.
Implementation Method 1
An electrostatic barrier layer is formed within the fin to create vertical isolation
Data Source
AI summary
An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.