Semiconductor Isolation Structures with Asymmetric Charge Layers
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Solution Overview
Problem
Current semiconductor isolation structures fail to simultaneously reduce leakage current in P-type metal oxide semiconductor (PMOS) devices when turned off and avoid the hump effect in N-type metal oxide semiconductor (NMOS) devices.
Innovation Solution
A semiconductor isolation structure is formed with a substrate having trenches with specific charge layers: a fixed negative charge layer far from the sidewalls in the PMOS region and no fixed positive charge layer near the sidewalls in the NMOS region, along with a filling and liner layer configuration that reduces leakage current and prevents the hump effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional isolation structure is used, then the leakage current of PMOS devices can be reduced, but the hump effect in NMOS devices cannot be avoided
Solution Approach 1:
The patent applies different charge layer configurations to different device regions: the PMOS region has a fixed negative charge layer positioned away from the trench sidewall to reduce leakage, while the NMOS region has a fixed positive charge layer positioned near the trench sidewall to prevent the hump effect. This local differentiation allows each device type to have optimized isolation characteristics without compromising the other.
2Object-affected harmful factors
If a fixed negative charge layer is positioned near the trench sidewall to reduce PMOS leakage, then leakage current decreases, but the hump effect in NMOS devices is exacerbated
Solution Approach 1:
The patent creates an asymmetric charge layer configuration where the fixed negative charge layer is positioned at different distances from the trench sidewall in PMOS regions versus NMOS regions. In PMOS regions, the negative charge layer is positioned farther from the sidewall to minimize leakage, while in NMOS regions, a fixed positive charge layer is positioned near the sidewall to counteract the hump effect, creating a non-uniform but optimized isolation structure.
3Ease of manufacture
If a single uniform isolation structure is used across all device regions, then manufacturing complexity is reduced, but device performance cannot be optimized for both PMOS and NMOS devices
Solution Approach 1:
The patent divides the isolation structure into region-specific segments with different charge layer configurations. The substrate is segmented into PMOS regions and NMOS regions, each receiving tailored charge layers: fixed negative charge layers for PMOS isolation and fixed positive charge layers for NMOS isolation. This segmentation allows independent optimization of each device type's electrical characteristics while maintaining a unified manufacturing process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current in PMOS devices and avoids the hump effect in NMOS devices, enhancing the reliability of CMOS devices and compatibility with memory processes.
Implementation Method 1
a fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench; and a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench
Data Source
AI summary
Provided is a semiconductor isolation structure including: a substrate having a first trench in a first region of the substrate and a second trench in a second region of the substrate; a filling layer is located in the first trench and the second trench; a liner layer on the sidewalls and bottom of the first trench and the second trench; a fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench; and a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench. The liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure. The liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure.