Active Gate Contacts for FinFET Layout Density
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Solution Overview
Problem
Conventional semiconductor device fabrication techniques waste layout space by contacting gate electrodes over isolation regions, reducing device density.
Innovation Solution
A method involving forming source/drain and gate contacts directly over active gate structures, including steps like forming gate structures over a fin substrate, creating raised source/drain structures, trench silicide formation, conformal metal oxide liner deposition, and interlayer dielectric layer formation to enable contact formation directly over the gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If contacts are formed over isolation regions as in conventional fabrication techniques, then the fabrication process is simpler, but layout space is wasted and device density is reduced
Solution Approach 1:
The patent transitions from planar contact formation to three-dimensional contact formation by etching through multiple layers (ILD, cap layer, gate electrode) to reach the active gate structure. This vertical dimensionality change enables contacts to be formed directly over the functional portion of the gate, maximizing layout space utilization while maintaining fabrication feasibility through standardized etching and deposition processes
2Area of stationary object
If contacts are formed directly over active gate structures, then device density is improved, but fabrication complexity increases due to additional process steps
Solution Approach 1:
The patent performs preliminary actions by forming the gate electrode structure and isolation regions with sufficient height and overhang before contact formation. The gate electrode is extended beyond the isolation region boundaries, and the ILD layer is planarized to create a stable platform. These preliminary structures enable subsequent contact etching to reach the active gate portion directly, simplifying the overall process despite the complex final structure
Solution Approach 2:
The contact formation process is segmented into distinct stages: forming the gate structure with overhang, depositing cap layers, creating ILD layers, and finally etching contacts through specific paths. This segmentation allows each step to be optimized independently, managing fabrication complexity while achieving the goal of direct contact over active gates
3Productivity
If conventional contact formation over isolation regions is used, then process steps are fewer, but device performance and integration efficiency are adversely affected
Solution Approach 1:
The patent applies local quality by forming contacts with different paths and structures depending on their location. Contacts over active gates follow one etch path through the gate electrode, while other contacts follow different paths. The gate electrode itself has different portions (active vs. non-active) that require different contact approaches. This localized differentiation maximizes device integration efficiency by optimizing each contact for its specific function while managing overall process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device density and performance by allowing direct contact over active gate structures, improving integration and yield.
Implementation Method 1
forming a metal oxide liner of aluminum oxide (Al2O3), titanium dioxide (TiO2) or hafnium oxide (HfO2) by atomic layer deposition (ALD)
Data Source
AI summary
A method of forming contacts over active gates is provided. Embodiments include forming first and second gate structures over a portion of a fin; forming a first and second RSD in a portion of the fin between the first gate structures and between the first and the second gate structure, respectively; forming TS structures over the first and second RSD; forming a first cap layer over the first and second gate structures or over the TS structures; forming a metal oxide liner over the substrate, trenches formed; filling the trenches with a second cap layer; forming an ILD layer over the substrate; forming a CA through a first portion of the ILD and metal oxide layer down to the TS structures over the second RSD; and forming a CB through a second portion of the ILD and metal oxide layer down to the first gate structures.