Semiconductor Chip Pseudo Bump Redistribution Interconnect
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Solution Overview
Problem
Conventional redistribution processes for semiconductor chips, such as flip-chip bonding, require additional photolithography and plating processes, increasing processing time and costs while aiming to enhance power/ground characteristics.
Innovation Solution
The implementation of pseudo bumps on a passivation film, connected to form redistribution interconnects, which include UBM layers and solder layers, allowing direct connection and reducing the need for additional processing steps, thereby improving power/ground characteristics without extra costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional redistribution processes are used to enhance power/ground characteristics, then power/ground characteristics are improved, but processing time and costs increase due to additional photolithography and plating processes
Solution Approach 1:
The patent extracts the redistribution function from the conventional photolithography and plating processes, implementing it instead through directly connected pseudo bumps formed by bumping processes alone. This removes the need for additional photolithography and plating steps while maintaining the power/ground redistribution capability, thus resolving the contradiction between improved power/ground characteristics and reduced processing time
Solution Approach 2:
The patent merges the bump formation process with the redistribution interconnect formation by directly connecting pseudo bumps to each other. This combines what were previously separate processes (bump formation and redistribution layer creation) into a single integrated approach, eliminating additional processing steps and reducing overall processing time while maintaining electrical connectivity
2Reliability
If conventional redistribution processes are used to enhance power/ground characteristics, then power/ground characteristics are improved, but processing costs increase due to additional photolithography and plating processes
Solution Approach 1:
The patent extracts the redistribution function from the conventional photolithography and plating processes, implementing it instead through directly connected pseudo bumps formed by bumping processes alone. This removes the need for additional photolithography and plating steps while maintaining the power/ground redistribution capability, thus resolving the contradiction between improved power/ground characteristics and reduced processing time
Solution Approach 2:
The pseudo bumps serve multiple functions: they act as both connection elements and redistribution interconnects. This multi-functionality eliminates the need for separate redistribution layers and associated processing steps, reducing manufacturing complexity and cost while achieving the desired power/ground characteristics
3Loss of time
If pseudo bumps are directly connected to form redistribution interconnects, then processing time and costs are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs a two-stage bumping process with reflow that allows dynamic adjustment and self-alignment. The first bumping process creates initial pseudo bumps, then reflow enables them to spread and connect to adjacent bumps, providing a degree of self-correction for alignment variations. This dynamic process reduces the stringency of initial alignment requirements compared to static single-step processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances power/ground characteristics by directly connecting pseudo bumps and through-bumps, reducing resistance and inductance, and allows for more flexible pad layouts without additional processing, thus improving the efficiency and cost-effectiveness of semiconductor chip manufacturing.
Implementation Method 1
a plurality of first UBM layers have intervals therebetween, such that first solder layers are disposed to cover the plurality of first UBM layers and the intervals therebetween to directly connect adjacent first solder layers
Data Source
AI summary
A semiconductor chip includes a redistribution interconnect that is implemented by shorting bumps, and a semiconductor package and a system each including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a passivation film disposed on the semiconductor substrate, and a plurality of pseudo bumps disposed on the passivation film. Each pseudo bump is directly connected to adjacent pseudo bumps to form at least one redistribution interconnect.