Semiconductor Package Flip-Chip Stacking Gate Electrode
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Solution Overview
Problem
The challenge is to miniaturize and thin semiconductor device packages while reducing on-resistance values for portable apparatus, particularly in lithium ion battery protection circuits, where conventional configurations face difficulties in stacking ICs and managing large currents effectively.
Innovation Solution
A semiconductor device is designed with a flip-chip mounting configuration, where semiconductor chips with transistors are mounted on a frame, and IC chips are stacked on top, connected via metal wires, allowing for efficient electrical connections and package miniaturization by exposing gate electrodes along the package sides and using a common drain electrode to reduce on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional mounting configurations are used with chips arranged side by side on the lead frame, then the package structure is simple to manufacture, but the package size cannot be miniaturized and on-resistance values cannot be reduced
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side arrangement of chips on the lead frame to a three-dimensional stacked configuration where the IC chip is mounted on top of the power MOSFET chips. This vertical stacking enables package miniaturization by utilizing the Z-axis dimension, reducing the horizontal footprint while maintaining all necessary electrical connections through wire bonds connecting multiple layers.
Solution Approach 2:
The IC chip is nested on top of the power MOSFET chips, creating a hierarchical layered structure. The control functionality is embedded within the power switching structure, allowing the entire protection circuit to be contained in a compact package. This nesting approach integrates multiple functional chips into a single cohesive unit, reducing overall package size.
2Reliability
If wire bonds are used to connect source electrodes for large current, then the manufacturing process is simple, but the on-resistance value increases and current handling capability is limited
Solution Approach 1:
Multiple source electrodes from different power MOSFET chips are merged and connected to a common source terminal on the lead frame. This consolidation creates a low-resistance current path by combining parallel conductive paths, significantly reducing the total on-resistance compared to individual wire bonds. The merged connection structure efficiently handles large currents by distributing the current load across multiple bonded electrodes.
Solution Approach 2:
A common source terminal on the lead frame serves as an intermediary node that collects current from multiple power MOSFET source electrodes. This intermediary structure provides a low-resistance aggregation point that simplifies the external connection while maintaining low on-resistance internally, acting as a current hub that efficiently routes large currents to the package terminals.
3Productivity
If multiple separate packages are used for power MOSFETs and protection IC, then each component can be optimized independently, but the overall assembly size increases and integration density decreases
Solution Approach 1:
The patent merges the power MOSFET chips and the protection IC into a single integrated package. The control chip and power switching chips are mounted together on the same lead frame, creating a unified protection circuit module. This integration increases productivity by reducing the number of separate components and assembly steps, while the modular chip design within the package maintains the ability to optimize each component independently for its specific function.
Data Source
AI summary
The present invention provides a semiconductor device that can achieve miniaturization or thinning of the size of the package while maintaining the characteristic of the MOSFET and reducing the on-resistance value, and a portable apparatus using the same. The gate electrodes 26 and 28 of the semiconductor chip 10 are disposed in the vicinity of the two side surfaces of the longitudinal direction (the x axis direction on the page) of the package 2, and the gate terminal 13 and 14 that is mounted with the gate electrodes 26 and 28 in a flip-chip manner are extended in the longitudinal direction of the package 2 and are derived to the outside from the two side surfaces 2A and 2B. Based on the configuration, it is capable of maximizing the size of the semiconductor chip with respect to the size of the package, and it is able to realize the high performance of the element characteristic for the module.