Integrally Forming Electrical Fuse and MOS Transistor

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Solution Overview

Problem

The advancement of semiconductor manufacturing technology, particularly the inclusion of metal structures in MOS device gate electrodes, poses a challenge for constructing electrical fuse devices without increasing fabrication costs, as separate processing steps are often required, leading to increased costs.

Innovation Solution

A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate by depositing and patterning a dielectric layer, a metal layer, and a polysilicon layer, allowing the electrical fuse device and the MOS device to share processing steps, including the use of a metal gate structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate processing steps are used to construct the MOS device and the electrical fuse device, then the MOS device can have a metal gate structure, but the fabrication costs will increase

Engineering Contradiction:

Improvemetal gate structure compatibilityVSAvoidfabrication cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent merges the formation of the electrical fuse device and the MOS device into a single integrated process. The metal layer and polysilicon layer are deposited once and then selectively patterned to form both the fuse device (on isolation structure) and the MOS device gate (on semiconductor substrate) simultaneously, eliminating the need for separate processing steps and reducing fabrication costs.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The deposited metal layer and polysilicon layer serve dual functions: they form the gate structure for the MOS device and simultaneously form the fuse device structure. This multi-functional approach allows a single processing sequence to accomplish what would traditionally require separate processes, maintaining metal gate compatibility while controlling costs.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Ease of manufacture

If the same polysilicon layer is used for both the electrical fuse device and the MOS device gate, then processing steps can be shared, but the MOS device cannot include a metal structure in its gate electrode

Engineering Contradiction:

Improveprocessing step integrationVSAvoidmetal gate structure capability

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent segments the patterned metal layer and polysilicon layer into two distinct functional regions: one region forms the electrical fuse device on the isolation structure, while another region forms the MOS device gate on the semiconductor substrate. This segmentation allows each structure to be optimized independently while sharing the same deposition process.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent adds a dimensional aspect by creating separate spatial zones for the fuse device and MOS device gate within the same deposited layers. By utilizing different locations (on isolation structure vs. on semiconductor substrate), the solution enables both structures to coexist with different material compositions - metal for the MOS gate and polysilicon for the fuse device.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables the construction of electrical fuse devices and MOS devices with metal gate structures in a single series of processing steps, reducing fabrication costs and maintaining compatibility with advanced semiconductor manufacturing processes.

Implementation Method 1

A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer.

Methodology Applied

Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS7534671B2Method for integrally forming an electrical fuse device and a MOS transistor

Publication Date: 2009.05.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer. The dielectric layer, the metal layer and the polysilicon layer are patterned into a first stack of the dielectric layer, the metal layer and the polysilicon layer on the isolation structure for functioning as the electrical fuse device, and a second stack of the dielectric layer, the metal layer and the polysilicon layer on the semiconductor substrate for functioning as a gate of the MOS device.