Floating Gate Spacer for Source Implant Control

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Solution Overview

Problem

In scaled-down memory cells, the source region dopant diffuses excessively laterally, and the floating gate tips are unprotected during the high-voltage ion implant process, leading to undesirable rounding and loss of sharpness, as well as inadequate control over the source junction edge location.

Innovation Solution

A non-conformal, self-aligned floating gate spacer is used, with spacer sidewall regions that prevent source implant material penetration and control the lateral extent of the source region, protecting the floating gate tips and allowing independent lateral control of the source junction edge.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a high-voltage ion implant process is used to form the source region, then the source dopant can be effectively implanted into the substrate, but the source dopant diffuses excessively laterally underneath the floating gate

Engineering Contradiction:
Improvesource dopant implantationVSAvoidlateral diffusion control
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

A spacer layer is formed over the floating gate structure before the high-voltage ion implant process. This preliminary spacer structure serves as a mask that prevents source dopant from diffusing laterally underneath the floating gate during implantation, while still allowing effective vertical implantation into the substrate through openings in the spacer layer.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The spacer layer acts as an intermediary element between the floating gate and the source dopant. It provides a protective barrier that controls the interaction between the dopant and the floating gate structure, enabling precise control over lateral diffusion while maintaining effective dopant implantation in the substrate.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If the floating gate tips are left exposed during high-voltage ion implant, then the implant process can proceed without additional masking steps, but the floating gate tips become unprotected and experience rounding

Engineering Contradiction:
Improveimplant process simplicityVSAvoidfloating gate tip sharpness
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The spacer layer is formed in advance over the floating gate structure, including the tips, before the high-voltage ion implant process. This preliminary protective layer shields the floating gate tips from dopant penetration that would cause rounding, while the implant process itself remains straightforward without requiring additional complex masking steps.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If the source region is formed before the word lines and coupling gate, then the source implant can be performed through a simple opening in resist, but independent lateral control of the source junction edge location is lost

Engineering Contradiction:
Improvesource implant processVSAvoidsource junction edge location control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The spacer layer serves as an intermediary structure that enables independent control of the source junction edge location. By adjusting the spacer layer thickness and pattern, precise control over where the source region terminates laterally is achieved, decoupling this critical dimension from the word line and coupling gate formation processes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The non-conformal spacer layer effectively reduces lateral diffusion of the source region, prevents rounding of the floating gate tips, and provides precise control over the source junction edge location, essential for hot carrier injection programming in shrunk memory cells.

Implementation Method 1

The spacer sidewall region substantially prevents penetration of source implant material

Methodology Applied
Scientific EffectPhysical barrier (diffusion barrier): Diffusion Barrier

Implementation Method 2

The source implant material diffuses laterally to extend partially under the floating gate

Methodology Applied
Scientific EffectLateral diffusion: Diffusion

Data Source

PatentUS10424589B2Floating gate spacer for controlling a source region formation in a memory cell
Publication Date: 2019.09.24 MICROCHIP TECHNOLOGY INC
  • US10424589B2 patent drawing
  • US10424589B2 patent drawing
  • US10424589B2 patent drawing

AI summary

A method is provided for forming an integrated circuit memory cell, e.g., flash memory cell. A pair of spaced-apart floating gate structures may be formed over a substrate. A non-conformal spacer layer may be formed over the structure, and may include spacer sidewall regions laterally adjacent the floating gate sidewalls. A source implant may be performed, e.g., via HVII, to define a source implant region in the substrate. The spacer sidewall region substantially prevents penetration of source implant material, such that the source implant region is self-aligned by the spacer sidewall region. The source implant material diffuses laterally to extend partially under the floating gate. Using the non-conformal spacer layer, including the spacer sidewall regions, may (a) protect the upper corner, or “tip” of the floating gate from rounding and (b) provide lateral control of the source junction edge location under each floating gate.