Three-Terminal NMOS NVM Cell with Asymmetric Floating Gate
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Solution Overview
Problem
Existing CMOS process flows are inefficient for producing non-standard circuit components like non-volatile memory cells, requiring significant modifications and additional steps, which are costly and disrupt standard circuit elements.
Innovation Solution
Development of medium-sized, three-terminal NMOS non-volatile memory cells using a standard or slightly modified single-poly CMOS process flow, incorporating two NMOS transistors with a shared drain region and floating gate, and employing techniques like low-voltage and high-voltage LDD implants and channel-hot-electron programming to enhance endurance and reduce program/erase times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard CMOS process flow is used to produce non-volatile memory cells, then manufacturing cost is reduced and process compatibility is improved, but program/erase time is excessive and endurance is limited
Solution Approach 1:
The patent applies local quality by implementing different LDD implantation strategies in different regions of the injection transistor. Specifically, the drain region receives high-voltage LDD implants to enhance hot carrier generation for faster programming, while the source region receives low-voltage LDD implants to optimize erase performance. This localized differentiation of doping characteristics enables simultaneous optimization of both program and erase operations without requiring complete process redesign.
Solution Approach 2:
The patent utilizes parameter changes by modifying the LDD implantation parameters (voltage, dose, depth) in specific regions to achieve desired performance characteristics. By adjusting the implantation energy and concentration profiles in the drain and source regions separately, the invention optimizes the electric field distribution and carrier injection efficiency, thereby reducing program/erase times while maintaining compatibility with standard CMOS processes.
2Reliability
If additional process steps and masks are added to produce non-standard circuit components, then device performance is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent applies universality by designing the non-volatile memory cell to share common structures and process steps with standard CMOS circuits. The injection transistor, read transistor, and floating gate are integrated using the same polysilicon gate layer and doping processes that define the CMOS platform. This multi-functionality approach allows the NVM cell to be manufactured alongside standard logic circuits using essentially the same process toolkit, minimizing additional complexity.
Solution Approach 2:
The patent merges the NVM cell structure with standard CMOS transistor architecture by combining the floating gate with the polysilicon gate layer already present in CMOS technology. The injection transistor and read transistor are formed using identical process sequences, and the shared drain region integrates both transistor functions. This merging eliminates the need for separate fabrication lines or entirely new process modules.
3Ease of manufacture
If symmetric floating gate coupling is used in PMOS NVM cells, then manufacturing simplicity is maintained, but erase operation becomes practically impossible and application is limited to OTP memories
Solution Approach 1:
The patent applies asymmetry by creating an asymmetric floating gate coupling configuration where the injection transistor's drain region is capacitively coupled to the floating gate with significantly stronger coupling than the read transistor's drain. This asymmetric coupling is achieved through geometric design (injection transistor drain positioned closer to or overlapping more of the floating gate) and is essential for enabling both program and erase operations. The asymmetric structure allows sufficient voltage transfer during erase operations, which was impossible with symmetric coupling in PMOS implementations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for high-endurance, cost-effective integration of non-volatile memory cells into CMOS ICs with minimal disruption to standard CMOS processes, achieving superior performance with suppressed read disturb effects and efficient programming/erasing operations.
Implementation Method 1
a floating gate capacitively coupled to the drain area
Implementation Method 2
employing techniques like low-voltage and high-voltage LDD implants and channel-hot-electron programming to enhance endurance and reduce program/erase times
Data Source
AI summary
A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by either a standard CMOS process flow or a slightly modified CMOS process flow. The NVM cell includes read and injection transistors that share a common floating gate. The floating gate includes a portion disposed over the channel region of the read transistor, a portion disposed over the channel region of the injection transistor, and a portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. The source/drain of the injection transistor are formed using different LDD implants to achieve faster program/erase. Alternatively, an optional CHE enhancing implant is added to the source/drain of the injection transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension.