Vertically Stacked Transistors for SRAM Area Reduction
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Solution Overview
Problem
The challenge in semiconductor technology is to reduce the memory cell area without compromising performance and function, particularly in memory devices where scaling increases fabrication difficulty and energy consumption, while maintaining performance and density requirements.
Innovation Solution
The solution involves a semiconductor device with vertically stacked transistors that share common channels, interconnect layers, and electrical connections, allowing for a reduced footprint and simplified manufacturing processes, such as using junction-less transistors and gate-all-around field-effect transistors (GAA FETs) with vertically aligned nanowires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional planar transistors are used to reduce memory cell area, then device footprint is reduced, but fabrication difficulty and energy consumption increase
Solution Approach 1:
The patent transitions from planar 2D transistor architecture to vertical 3D transistor architecture. The channel extends vertically from the substrate surface, allowing multiple memory devices to be stacked in the vertical dimension. This dimensional change enables area reduction while maintaining fabrication feasibility, as the vertical structure allows for shared common channels and interconnect layers between stacked devices.
2Area of stationary object
If transistor scaling is continued to reduce memory cell area, then density increases, but performance and energy consumption criteria deteriorate
Solution Approach 1:
By moving to vertical transistors, the gate can wrap around the channel in three dimensions (gate-all-around configuration), providing superior electrostatic control compared to planar gates. This enhanced control maintains device performance at scaled dimensions. Additionally, the vertical architecture enables stacking of multiple memory devices sharing common channels, achieving area reduction without the performance degradation typically associated with aggressive scaling.
3Device complexity
If vertically stacked memory devices share common channels, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges multiple memory devices vertically by having them share common channels and interconnect layers. Adjacent memory devices share bitlines and wordlines, reducing the total number of interconnect layers needed. This merging approach reduces overall device complexity while the common channel structure provides natural alignment references that help manage precision requirements during fabrication.
Data Source
AI summary
The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.