Dual Capping Layers for NMOS PMOS Strain Engineering
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Solution Overview
Problem
Current polysilicon cap layers with high tensile stress improve NMOS device performance but degrade PMOS device performance during source and drain anneal, necessitating a method to introduce tensile strain into NMOS devices without affecting PMOS devices.
Innovation Solution
The method involves forming source and drain regions in NMOS and PMOS semiconductor devices using dual capping layers and split thermal processes, where a tensile stress capping layer is applied to NMOS regions and a compressive stress capping layer is applied to PMOS regions, allowing for individual optimization of each device type during re-crystallization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single thermal process is used to anneal both NMOS and PMOS devices simultaneously, then processing time is reduced, but the PMOS device performance is adversely affected by the tensile stress from the polysilicon cap layer
Solution Approach 1:
The patent divides the simultaneous annealing process into two sequential annealing steps: first annealing NMOS devices with tensile stress, then annealing PMOS devices with compressive stress. This segmentation prioritizes device performance over processing speed, accepting the trade-off of additional processing time to avoid PMOS degradation.
Solution Approach 2:
The patent performs the NMOS annealing with tensile stress as a preliminary action before the PMOS annealing. This preliminary action ensures that NMOS devices receive their required tensile strain treatment before the polysilicon cap layer is replaced with a compressive stress layer for PMOS annealing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the introduction of tensile strain in NMOS devices while avoiding adverse effects on PMOS devices, allowing for optimized performance of both device types without mutual interference during processing.
Implementation Method 1
forming a tensile stress capping layer over the at least one NMOS semiconductor region and at least one PMOS semiconductor region; performing a thermal process to re-crystallize the source region and drain region of the NMOS semiconductor region and to introduce tensile strain to the source region and drain region of the NMOS semiconductor region
Implementation Method 2
forming a compressive stress capping layer over the at least one PMOS semiconductor region and at least one NMOS semiconductor region; performing a thermal process to re-crystallize the source region and drain region of the PMOS semiconductor region and to introduce compressive strain to the source region and drain region of the PMOS semiconductor region
Implementation Method 3
performing a thermal process to re-crystallize the source region and drain region
Implementation Method 4
performing a thermal process to re-crystallize the source region and drain region
Data Source
AI summary
Source and drain regions are formed in a first-type semiconductor device. Then, a high tensile stress capping layer is formed over the source and drain regions. A thermal process is then performed to re-crystallize the source and drain regions and to introduce tensile strain into the source and drain regions of the first-type semiconductor device. Afterwards, source and drain regions are formed in a second-type semiconductor device. Then, a high compressive stress capping layer is formed over the source and drain regions of the second-type semiconductor device. A thermal process is performed to re-crystallize the source and drain regions and to introduce compressive strain into the source and drain regions of the second-type semiconductor device.