Non-volatile Memory High Resistance Region for Low Voltage Writing
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Solution Overview
Problem
Conventional non-volatile semiconductor memory devices face challenges in reducing circuit size due to high voltage requirements for data writing and erasing, leading to increased film thickness and overall circuit size, with existing devices being used primarily as OTPs due to difficulty in extracting carriers from the carrier storage region.
Innovation Solution
A non-volatile semiconductor memory device with a single-layer gate structure featuring a high resistance region between the channel and drain regions, allowing carrier injection into the carrier storage region via a strong electric field generated in the high resistance region, reducing the voltage needed for data writing and enabling thinner gate insulating films, thus minimizing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high voltage of 5 to 7 V is applied to the gate electrode to inject carriers into the carrier storage region, then data can be written into the memory device, but the film thickness of the gate insulating film needs to be increased, resulting in increased cell size
Solution Approach 1:
The patent introduces a high resistance region specifically in the drain extension area, creating a localized zone with different electrical properties. This high resistance region generates a concentrated electric field that enables carrier injection at lower voltages, eliminating the need to increase gate insulating film thickness across the entire device.
Solution Approach 2:
The patent changes the resistance parameter by forming a high resistance region through controlled impurity doping in the drain extension area. This parameter change creates a strong electric field in a localized region, allowing carrier injection at lower gate voltages (1.5-3.0 V) compared to conventional devices requiring 5-7 V.
2Reliability
If a high voltage of 5 to 7 V is controlled for each bit line to inject carriers, then data can be written, but peripheral transistors must also be formed as high-voltage elements with larger gate insulating film thickness, increasing the overall circuit size
Solution Approach 1:
The high resistance region is localized in the drain extension area of the memory transistor, creating a focused electric field generation zone. This localized approach allows carrier injection functionality to be achieved without requiring all peripheral transistors to be designed as high-voltage elements, thus reducing overall circuit area.
Solution Approach 2:
The patent segments the voltage function by concentrating the high electric field generation in a specific region (drain extension with high resistance) rather than requiring high voltage across the entire circuit. This segmentation allows peripheral transistors to operate at lower voltages with smaller dimensions.
3Strength
If the gate insulating film thickness is increased to withstand high voltage, then high voltage operation is enabled, but the cell size and overall device dimensions are increased
Solution Approach 1:
Instead of increasing gate insulating film thickness throughout the device to withstand high voltage, the patent creates a localized high resistance region that generates sufficient electric field at lower voltages. This approach maintains voltage withstanding capability while avoiding the volume increase that would result from thicker insulating films across the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for reduced voltage application to bit lines and gate electrodes, resulting in a smaller circuit configuration and efficient data writing without the need for high-voltage elements, facilitating the use of standard CMOS processes for manufacturing.
Implementation Method 1
a strong electric field generated in the high resistance region
Implementation Method 2
carriers in the drain region can be injected into the carrier storage region via the high resistance region by source side injection
Data Source
AI summary
In a non-volatile semiconductor memory device, it is only necessary that, at the time of data writing, a voltage drop is caused in a high resistance region. Therefore, the value of voltage applied to a gate electrode can be reduced as compared with a conventional device. In correspondence with the reduction in the value of applied voltage, it is possible to reduce the film thickness of a gate insulating film of memory transistors, and further the film thickness of the gate insulating film of a peripheral transistor for controlling the memory transistors. As a result, the circuit configuration of the non-volatile semiconductor memory device can be reduced in size as compared with the conventional device.