Integrating Vertical and 3D Transistors via Shared Fin Patterning
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Solution Overview
Problem
The challenge in semiconductor processing lies in integrating vertical transistors with short gate lengths and three-dimensional channel transistors, as existing methods face difficulties in fabricating diverse gate lengths required for logic and analog FETs on the same chip, leading to complex topography and increased chip size due to separate processing requirements.
Innovation Solution
The method involves forming narrow and wide fins in a substrate, depositing source/drain regions, and patterning gate dielectric and conductor layers to create vertical and three-dimensional gate structures, sharing common processes to integrate vertical and 3D transistors, reducing manufacturing costs and chip size by exploiting shared elements and processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate processing is used for vertical transistors and 3D long channel transistors, then each transistor type can be optimized independently, but chip size increases and manufacturing complexity increases
Solution Approach 1:
The patent merges the processing of vertical transistors and 3D long channel transistors into a unified fabrication sequence. Common steps include forming fins with different widths, depositing gate dielectric and conductor layers, forming gate structures, and creating source/drain regions. This integration allows both transistor types to coexist on the same chip without requiring separate processing lines, thereby reducing chip size while maintaining manufacturing precision through standardized processes.
Solution Approach 2:
The patent creates a universal processing methodology that handles both vertical and 3D long channel transistors using the same fabrication techniques. The fin formation process, gate deposition, and source/drain engineering are designed to accommodate both transistor architectures simultaneously. This multi-functional approach enables a single chip to host diverse transistor types optimized for different functions (logic vs. analog) without increasing manufacturing complexity.
2Manufacturing precision
If separate processing is used for vertical transistors and 3D long channel transistors, then each transistor type can be optimized independently, but device density decreases
Solution Approach 1:
By combining the fabrication processes for vertical and 3D long channel transistors into a single integrated sequence, the patent enables higher device density. The unified approach allows closer packing of different transistor types on the same chip area, as both can be formed simultaneously during the same processing cycles. This eliminates the need for separate dedicated areas for each transistor type, thereby increasing overall device density while maintaining independent optimization capabilities.
3Adaptability or versatility
If different gate lengths are fabricated on the same chip, then logic and analog FETs can be integrated, but topography complexity increases
Solution Approach 1:
The patent applies local quality by creating regions with different fin widths on the same chip. Narrow fins are formed for vertical transistors requiring short gate lengths for logic operations, while wide fins are formed for 3D long channel transistors requiring longer gate lengths for analog operations. This localized differentiation allows diverse transistor characteristics to coexist without requiring complex topography management, as the fin width variation is achieved through a single patterning step rather than multiple complex lithography processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the integration of logic and analog FETs on the same chip, reducing chip size and increasing device density by utilizing shared processes, while maintaining efficient manufacturing costs and design integration.
Implementation Method 1
forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin
Implementation Method 2
forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin
Implementation Method 3
epitaxially growing a first source/drain region (S/D) at a base of the narrow fin
Implementation Method 4
implanting dopants to form wells in a substrate
Data Source
AI summary
A method for integrating a vertical transistor and a three-dimensional channel transistor includes forming narrow fins and wide fins in a substrate; forming a first source/drain (S/D) region at a base of the narrow fin and forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin. The gate conductor layer and the gate dielectric layer are patterned to form a vertical gate structure and a three-dimensional (3D) gate structure. Gate spacers are formed over sidewalls of the gate structures. A planarizing layer is deposited over the vertical gate structure and the 3D gate structure. A top portion of the narrow fin is exposed. S/D regions are formed on opposite sides of the 3D gate structure to form a 3D transistor, and a second S/D region is formed on the top portion of the narrow fin to form a vertical transistor.