Vertical Channel Non-Volatile Memory Cell Structure for High Density
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Solution Overview
Problem
Current non-volatile memory devices face challenges in achieving high integration and density due to complex fabrication processes and the need for larger memory cells, which hinders their miniaturization and cost-effectiveness.
Innovation Solution
A non-volatile memory device with a vertical channel structure where a control gate, floating gate, and erase gate surround a part of the vertical channel, reducing the area required for each memory cell and allowing for increased density, and a manufacturing method that forms these gates and channels in a vertical configuration to enhance memory cell density and erase speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional horizontal memory cell structure is used, then the fabrication process is simpler, but the memory cell area is larger and density is lower
Solution Approach 1:
The patent transitions from a conventional horizontal planar memory cell structure to a vertical three-dimensional structure. The vertical channel extends in the vertical direction, and gates are arranged vertically around the channel, effectively utilizing the third dimension to reduce the footprint area of each memory cell while maintaining functional integrity.
Solution Approach 2:
The patent implements a nested gate structure where the control gate, floating gate, and erase gate are arranged concentrically around the vertical channel. The floating gate is surrounded by the control gate, and the erase gate is positioned between the substrate and floating gate, creating a nested configuration that maximizes space utilization.
2Quantity of substance
If memory cell density is increased through miniaturization, then larger capacity is achieved, but the fabrication process becomes more complicated
Solution Approach 1:
By moving to a vertical architecture, the patent achieves higher density without proportionally increasing fabrication complexity. The vertical channel and vertically-stacked gates can be formed using extended vertical processing techniques that build upon conventional planar processes, rather than requiring entirely new complex fabrication methodologies.
Solution Approach 2:
The patent divides the gate structure into three separate vertically-stacked components (control gate, floating gate, and erase gate) that can be formed and processed independently at different stages, allowing for modular fabrication that manages complexity while achieving high density.
3Area of stationary object
If the vertical channel structure with surrounding gates is used, then memory cell area is reduced and density is increased, but the device structure becomes more complex
Solution Approach 1:
The patent employs a nested gate configuration where gates are arranged concentrically around the vertical channel in a compact manner. This nested structure reduces the horizontal footprint while organizing complex components in a systematic vertical hierarchy, making the complexity more manageable through spatial organization.
Solution Approach 2:
The patent resolves structural complexity by transitioning to the vertical dimension, where multiple gates can be stacked and arranged around the channel without requiring large horizontal spacing. This vertical arrangement compactly houses complex components in a smaller overall footprint.
Data Source
AI summary
A non-volatile memory device includes a plurality of memory cells. Each memory cell includes a vertical channel, a control gate, a floating gate, and an erase gate disposed on a substrate. The vertical channel extends upwards in a vertical direction. The control gate, the floating gate, and the erase gate surround the vertical channel respectively, and a part of the floating gate is surrounded by the control gate. The erase gate is disposed between the substrate and the floating gate in the vertical direction, and the floating gate include a tip extending toward the erase gate. The vertical channel and electrodes surrounding the vertical channel, such as the control gate, the floating gate, and the erase gate, are used to reduce the area of the memory cell on the substrate of the non-volatile memory device in the present invention. The density of the memory cells may be enhanced accordingly.