Array Substrate With Variable Gate Dielectric Thickness
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Solution Overview
Problem
Current liquid crystal display technologies face challenges with poor viewing angles, particularly in fringe-field switching (FFS) and in-plane switching (IPS), where FFS offers higher transmittance and larger viewing angles but suffers from slow twist rate and low aperture ratio, necessitating more backlights.
Innovation Solution
The array substrate design incorporates a fringe-field switching technology with a gate dielectric layer having different thickness regions to reduce chaotic electric fields and improve liquid crystal efficiency, featuring a structure with interlaced scan and data lines, thin film transistors, and transparent electrodes, where the gate dielectric layer's terrain helps in minimizing parasitic capacitance and enhancing transmittance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If FFS technology is used to achieve higher transmittance and larger viewing angles, then transmittance and viewing angle are improved, but slow twist rate and low aperture ratio occur
Solution Approach 1:
The gate dielectric layer is designed with different thicknesses in different regions: a first thickness in the first region, a second thickness in the second region, and a third thickness in the third region. This local variation in thickness optimizes the electric field distribution specifically in the pixel region while maintaining proper transistor operation, thereby improving liquid crystal response speed without sacrificing transmittance
Solution Approach 2:
The patent introduces a vertical dimension variation through the multi-region gate dielectric layer structure. By controlling the dielectric layer thickness in the vertical dimension across different horizontal regions, the patent achieves optimized electric field control that improves twist rate while maintaining the transmittance benefits of FFS technology
2Illumination intensity
If FFS technology is used to achieve higher transmittance and larger viewing angles, then viewing angle is improved, but low aperture ratio occurs
Solution Approach 1:
The gate dielectric layer thickness is locally optimized: the first region has a first thickness for transistor operation, the second region has a second thickness for electric field control, and the third region has a third thickness for pixel performance. This allows the pixel electrode to extend closer to the data line while maintaining proper electrical characteristics, thereby increasing aperture ratio without compromising transmittance
3Productivity
If chaotic electric fields are reduced to improve liquid crystal efficiency, then liquid crystal efficiency and transmittance are improved, but device complexity increases
Solution Approach 1:
The gate dielectric layer is segmented into three distinct regions with different thicknesses. This segmentation allows independent optimization of each region's function: the first region for transistor gate control, the second region for electric field management, and the third region for pixel electrode coupling. This reduces chaotic electric fields and improves liquid crystal efficiency while keeping the fabrication process manageable through standardized thin-film deposition techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances liquid crystal efficiency and transmittance by reducing chaotic rotations and parasitic capacitance, leading to improved viewing angles and reduced need for additional backlights, thus addressing the limitations of existing FFS and IPS technologies.
Implementation Method 1
This design enhances liquid crystal efficiency and transmittance by reducing chaotic rotations and parasitic capacitance
Implementation Method 2
The array substrate includes at least one first transparent electrode, a passivation layer, and at least one second transparent electrode... One of the first transparent electrode and the second transparent electrode is electrically connected to the drain as a pixel electrode, and the other of the first transparent electrode and the second transparent electrode is electrically connected to a common potential source as a common electrode
Data Source
AI summary
An array substrate includes a scan line, a data line, a thin film transistor, a first transparent electrode, a passivation layer, and a second transparent electrode. The scan line and the data line interlace to define a pixel region. The gate dielectric layer of the thin film transistor overlaps the scan line and the data line and extends to cover the pixel region. The gate dielectric layer has a first region, a second region, and a third region. The first region corresponds to the semiconductor layer of the thin film transistor. The second region connects the first region and the third region. The thickness of the second region is different from that of the third region. The first transparent electrode covers the gate dielectric layer in the pixel region. The passivation layer covers the thin film transistor and the first transparent electrode. The second transparent electrode covers the passivation layer.