BiCMOS Device Isolation Film Height Strategy
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Solution Overview
Problem
The erosion of shallow trench isolation (STI) layers during the formation of CMOS devices leads to a sagging silicide layer at the junctions, affecting the operating characteristics of bipolar transistors due to variations in emitter width and junction depth, especially in miniaturized CMOS devices where shallow junctions are prevalent.
Innovation Solution
A method where the device isolation film is formed taller than the substrate surface at the bipolar transistor region, preventing erosion and maintaining a consistent silicide layer height, thereby stabilizing emitter width and diode current characteristics, while ensuring accurate gate processing by maintaining a small height difference between the substrate and isolation film in the MOS transistor region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If STI layer is used as device isolation film, then device isolation is achieved, but the upper regions of STI layer are eroded during CMOS formation processes, causing silicide layer to sag at junction ends
Solution Approach 1:
The patent applies different height configurations of the device isolation film to different regions: in the bipolar transistor region, the isolation film is formed taller than the substrate surface to prevent erosion and silicide sagging, while in the MOS transistor region, the height difference is kept small to ensure accurate gate processing. This local differentiation resolves the contradiction by addressing the specific needs of each transistor type.
Solution Approach 2:
The device isolation film is formed with a height greater than the substrate surface in the bipolar transistor region before the silicide layer formation process. This preliminary height configuration prevents erosion during subsequent CMOS formation processes (oxidation, sidewall formation, silicide block formation), thereby preventing silicide layer sagging before the problem can occur.
2Reliability
If silicide layer is formed over diffusion region, then contact resistance is decreased, but emitter width varies due to silicide layer sagging, affecting bipolar transistor characteristics
Solution Approach 1:
The patent implements a region-specific isolation film height strategy: taller isolation film in bipolar transistor regions prevents silicide sagging and maintains consistent emitter width, while smaller height differences in MOS regions preserve gate processing accuracy. This local differentiation allows silicide layers to be formed on diffusion regions for low contact resistance without compromising emitter width consistency in bipolar transistors.
Solution Approach 2:
The device isolation film is preliminarily formed with enhanced height in bipolar transistor regions before silicide layer deposition. This preliminary structural preparation prevents the silicide layer from sagging during and after formation, thereby maintaining consistent emitter width and stable diode current characteristics while still allowing the silicide layer to reduce contact resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents silicide layer sagging and stabilizes emitter width, maintaining consistent diode current characteristics and processing accuracy, even in miniaturized CMOS devices with shallow junctions.
Implementation Method 1
the processes of oxidizing a gate insulating film, forming a sidewall, and forming a silicide block
Implementation Method 2
when a metal film 16 of Co, Ni, Pt or the like is formed over the surface of the P+ diffusion layer 10 and a silicide layer 18 is formed by the reaction between silicon and the metal film 16
Data Source
AI summary
In a BiCMOS device, a device isolation film separating the bipolar transistor region from the MOS region is taller than the substrate at least where it contacts the bipolar transistor region, and is preferably taller than the same layer where it contacts the MOS transistor region. This makes it possible to maintain the processing accuracy of a MOS transistor while stabilizing the diode current characteristics of the bipolar transistor.