Stacked Transistor Semiconductor Device for Neural Network Acceleration
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Solution Overview
Problem
The challenge is to create a semiconductor device that is both small in size and has low power consumption, while also reducing the area of peripheral circuits and minimizing parasitic capacitance, which is difficult due to the increased number of transistors and leakage current in ternary data storage and the frequency of data reading during product-sum operations in neural networks.
Innovation Solution
A semiconductor device with a CPU and accelerator that includes a first memory circuit, a driver circuit, and a product-sum operation circuit, where the first memory circuit has transistors with a metal oxide channel formation region and the product-sum operation circuit has transistors with a silicon channel formation region, stacked together, along with a backup circuit to retain data even when power is stopped, and bit lines are connected in a perpendicular configuration to reduce charge/discharge energy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ternary data is stored in an SRAM memory cell, then the number of transistors in a memory cell is increased, but downsizing of a semiconductor device becomes difficult
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to 3D vertical stacking architecture. Multiple memory cells are stacked in the vertical direction, allowing ternary data storage with increased transistor count while maintaining small footprint area. The bit lines extend in the vertical direction to connect stacked memory cells, enabling compact integration without increasing planar device area.
Solution Approach 2:
The patent implements nested structure where multiple memory cells are vertically nested within a compact area. Each memory cell contains transistors with source and drain regions arranged in nested configurations, with bit lines passing through multiple stacked cells. This nesting allows high-density ternary data storage without expanding the semiconductor device area.
2Length of moving object
If scaling down of the transistor advances, then the transistor size is reduced, but power consumption due to leakage current is increased
Solution Approach 1:
The patent applies different material qualities to different regions of the transistor structure. The channel formation region uses metal oxide semiconductor material with specific electrical characteristics optimized for low leakage current, while source and drain regions use different doping configurations. This local quality differentiation allows scaled-down transistors to maintain low power consumption despite reduced dimensions.
Solution Approach 2:
The patent employs composite material structure in the transistor, combining metal oxide semiconductor in the channel region with differently doped source and drain regions. This composite approach creates transistors with optimized electrical properties that reduce leakage current even at scaled dimensions, addressing the power consumption issue while maintaining small transistor size.
3Loss of energy
If the bit line is shortened for reducing the charge/discharge energy, then the area of a memory cell array is increased, but the area of peripheral circuits is significantly increased
Solution Approach 1:
The patent reorients bit lines from horizontal planar extension to vertical extension through stacked memory cells. This dimensional change shortens the effective bit line length for charge/discharge operations while containing the memory cell array area within a compact footprint. The vertical bit line configuration prevents significant increase in peripheral circuit area that would result from planar expansion.
4Length of moving object
If three-dimensional integration of memory cell arrays is employed, then the bit line is shortened, but parasitic capacitance is increased because of large spaces between connection portions
Solution Approach 1:
The patent implements tight nesting of stacked memory cells with minimal spacing between connection portions. The vertical stacking architecture places memory cells in close proximity, eliminating large spaces between connection portions that would generate parasitic capacitance. This nested configuration allows short bit lines while maintaining low parasitic capacitance through compact vertical integration.
Data Source
AI summary
A semiconductor device includes a CPU and an accelerator that includes a first memory circuit, a driver circuit, and a product-sum operation circuit. The first memory circuit includes a first data retention portion, a second data retention portion, and a data reading portion. The first data retention portion, the second data retention portion, and the data reading portion each include a first transistor. The first transistor contains a metal oxide in a channel formation region. First data stored in the first data retention portion and second data stored in the second data retention portion are each weight data input to the product-sum operation circuit. The product-sum operation circuit has a function of performing product-sum operation of the weight data and input data input through the driver circuit. The product-sum operation circuit and the driver circuit each include a second transistor. The second transistor contains silicon in a channel formation region. The first transistor and the second transistor are stacked.