Fin-Type High Voltage IC Devices with Graded Junctions
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Solution Overview
Problem
High voltage IC devices face challenges in leakage currents and require additional processing steps, which increase costs and complexity in fabrication.
Innovation Solution
The method involves forming silicon fins with graded voltage junctions, deep isolation trenches, and epitaxial layers to reduce leakage currents and enable high voltage operation, using FINFET type processes to fabricate high voltage IC devices with parallel or perpendicular orientations to the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage devices are fabricated using traditional processes, then breakdown voltage is achieved, but leakage current increases and additional processing steps are required
Solution Approach 1:
The device is divided into multiple fins (first plurality and second plurality) with deep isolation trenches between them, segmenting the current path and confining leakage currents to specific regions rather than allowing them to spread across the entire device structure
Solution Approach 2:
Different regions of the device have different doping concentrations - lightly-doped regions in the bulk substrate and heavily-doped regions at the fin surfaces, creating local variations in electrical properties that reduce leakage while maintaining breakdown voltage characteristics
2Reliability
If high voltage devices are fabricated using traditional processes, then breakdown voltage is achieved, but device complexity and processing steps increase
Solution Approach 1:
The fin structure serves multiple functions simultaneously: it provides the primary conduction path, enables graded doping profiles through vertical geometry, and works with deep isolation trenches to confine leakage currents, eliminating the need for separate high voltage device structures
Solution Approach 2:
The doping concentration is varied continuously through the fin structure using graded implants, changing from lightly-doped bulk regions to heavily-doped surface regions, which optimizes both breakdown voltage and leakage current characteristics in a single continuous profile rather than requiring multiple discrete doping steps
3Object-generated harmful factors
If graded voltage junctions are formed with multiple dopant concentrations, then leakage current is reduced, but manufacturing precision requirements increase
Solution Approach 1:
A dummy gate structure is formed before the graded dopant implantation process, serving as a mask that defines the precise implantation regions and protects areas that should not be doped, thereby simplifying the subsequent doping process and reducing precision requirements
Solution Approach 2:
The fin geometry itself enables the graded doping profile - the vertical structure naturally accepts varying dopant concentrations from bulk to surface, and the epitaxial growth process automatically creates the transition zones between different doping regions without requiring precise external control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes leakage currents and supports high voltage operations with optimized breakdown voltage and reduced processing complexity, applicable in various industrial applications including microprocessors and automotive systems.
Implementation Method 1
forming a graded voltage junction by implanting one or more concentration levels of a dopant into the substrate layer below each of the first and second pluralities of silicon fins
Implementation Method 2
forming an epitaxial layer onto the first and second pluralities of silicon fins to form merged source and drain fins
Data Source
AI summary
Methods for making high voltage IC devices utilizing a fin-type process and resulting devices are disclosed. Embodiments include forming two pluralities of silicon fins on a substrate layer, separated by a space, wherein adjacent silicon fins are separated by a trench; forming an oxide layer on the substrate layer and filling a portion of each trench; forming two deep isolation trenches into the oxide layer and the substrate layer adjacent to the two pluralities of silicon fins; forming a graded voltage junction by implanting a dopant into the substrate layer below the two pluralities of silicon fins; forming a gate structure on the oxide layer and between the two pluralities of silicon fins; implanting a dopant into and under the two pluralities of silicon fins, forming source and drain regions; and forming an epitaxial layer onto the two pluralities of silicon fins to form merged source and drain fins.