Flash Memory Layout Using Recessed and Horizontal Select Gate Channels
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Solution Overview
Problem
The increasing demand for smaller, more integrated flash memory in portable electronic devices poses a challenge for existing NAND flash memory layouts, which need to enhance integration and reduce size without compromising performance.
Innovation Solution
The proposed solution involves a NAND flash memory layout with dual gate transistors, where select gate transistors have recessed channels and horizontal channels, allowing for increased integration by providing a larger process window and enabling more compact design through optimized gate lengths and channel configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional NAND flash memory layout is used, then manufacturing process is simpler, but integration density and memory size reduction are limited
Solution Approach 1:
The patent applies asymmetry by implementing different channel configurations for different select gate transistors. Specifically, one select gate transistor has a recessed channel while another has a horizontal channel, breaking the symmetry of conventional layouts. This asymmetric design enables more compact arrangement of memory cell strings and select gates, thereby increasing integration density without requiring proportional increases in manufacturing complexity.
Solution Approach 2:
The patent utilizes dimensional optimization by transitioning from purely planar channel configurations to incorporating recessed channels that extend vertically into the substrate. This three-dimensional approach allows memory cell strings to be packed more densely by utilizing vertical space, effectively increasing integration density while maintaining manageable layout complexity through systematic arrangement.
2Quantity of substance
If more memory cells are integrated per unit area, then memory density increases, but space occupation per element increases
Solution Approach 1:
The patent implements nesting by placing memory cell strings in a shared well structure where multiple strings are vertically stacked and laterally arranged within a confined active area. The select gate transistors are nested around these memory cell strings, with their gates positioned to control multiple strings simultaneously. This nested configuration allows a high number of memory cells to be integrated per unit area while minimizing the space occupation of individual elements through efficient spatial utilization.
3Reliability
If select gate transistors use recessed channels, then process window increases and integration improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by implementing recessed channels only in specific select gate transistors where it provides the most benefit for process window and integration, while other select gate transistors use simpler horizontal channel configurations. This selective application of complex structures only where needed optimizes the process window and integration density without uniformly increasing manufacturing complexity across the entire device, thereby balancing reliability improvement with ease of manufacture.
Data Source
AI summary
A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.