Thin Film Transistor Non-Overlapping Gate and Semiconductor Layout
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Solution Overview
Problem
The manufacturing process of thin film transistors (TFTs) in TFT-LCDs often results in a large step difference between layers, leading to defects such as line disconnection due to the presence of multiple layers, which complicates the manufacturing process and increases the likelihood of cracks in the lines.
Innovation Solution
The solution involves reducing the number of layers in the TFT by ensuring that the projections of the gate electrode and semiconductor portion onto the substrate do not overlap, allowing for a simplified layer arrangement where the gate electrode, gate insulation portion, semiconductor portion, source electrode, and drain electrode are either all in the same layer or with the gate electrode directly on the substrate, and the semiconductor and electrodes in a separate layer, with a passivation layer covering them, and using notches or via holes to expose the electrodes for connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple layers are used in the TFT structure to ensure proper separation and connection of components, then the functional requirements are met, but the step difference between layers increases causing line disconnection and cracks
Solution Approach 1:
The patent transitions from a traditional multi-layer stacked structure to a planar structure where the gate electrode and semiconductor layer are arranged in the same layer rather than overlapping in vertical layers. This dimensional rearrangement eliminates the step difference between layers while maintaining the electrical connection reliability through proper spatial separation and connection design.
2Device complexity
If the gate electrode and semiconductor layer are arranged in overlapping layers, then the conventional TFT structure is maintained, but the step difference causes lines to crack and disconnect
Solution Approach 1:
Instead of following the conventional approach where the gate electrode is placed in a lower layer and the semiconductor layer is placed in an upper layer (overlapping vertically), the patent inverts this arrangement by placing both the gate electrode and semiconductor layer in the same horizontal plane. This inversion eliminates the vertical step difference that causes line cracking while maintaining the necessary electrical isolation and connection functions.
3Reliability
If six layers are provided in the TFT to ensure proper component separation, then the functional requirements are met, but the manufacturing process becomes complex and prone to defects
Solution Approach 1:
The patent merges the gate electrode and semiconductor layer into the same horizontal layer, eliminating the need for separate vertical layering. This consolidation reduces the total number of layers from six to three while maintaining proper component separation through planar arrangement and insulation design, thereby simplifying the manufacturing process and reducing defects.
Data Source
AI summary
The present disclosure provides a thin film transistor, a method for manufacturing the same, a thin film transistor assembly, an array substrate and a display apparatus. The thin film transistor comprises: a substrate; a gate electrode, a gate insulation portion, a semiconductor portion, a source electrode and a drain electrode, the gate insulation portion separating the semiconductor portion from the gate electrode, and the source electrode and the drain electrode being connected to the semiconductor portion, wherein a projection of the gate electrode onto the substrate and that of the semiconductor portion onto the substrate are not overlapped with each other.