Vertical Bipolar Injector for DRAM Memory Cell Area Reduction
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Solution Overview
Problem
Conventional floating body DRAM memory cells require high voltages for write operations, which can damage the cells and disrupt nearby memory cells, and have challenges in reducing surface area and accurately controlling substrate voltage, leading to potential disturbances between adjacent cells.
Innovation Solution
A memory cell design featuring a horizontal FET transistor with a bipolar transistor injector, where the emitter is integrated within the source and connected to an injection line below the surface, allowing for reduced surface area and controlled charge injection with lower voltages, thereby minimizing disturbances and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a horizontal bipolar transistor is used as injector with substrate as base, then the storage capacity is increased, but the surface area consumption increases and substrate voltage control becomes difficult
Solution Approach 1:
The patent transitions from a lateral horizontal bipolar transistor configuration to a vertical bipolar transistor configuration. The emitter is positioned below the source region, injecting charges vertically into the floating body through the source region which serves as the base. This vertical arrangement reduces surface area consumption while maintaining the charge injection function.
Solution Approach 2:
The vertical bipolar transistor structure is nested within the FET structure. The emitter of the bipolar transistor is integrated into or positioned directly below the source region of the FET, and the source region serves dual functions as both FET source and bipolar base. This nested configuration eliminates separate lateral structures, reducing overall cell area.
2Quantity of substance
If a horizontal bipolar transistor is used as injector, then the storage capacity is increased, but the voltage control of substrate base becomes inaccurate causing disturbances
Solution Approach 1:
By changing from lateral to vertical configuration, the base of the bipolar transistor is no longer the substrate but the source region of the FET. The source region voltage can be precisely controlled through the source line, enabling accurate bipolar base voltage control and eliminating substrate voltage control issues.
Solution Approach 2:
The bipolar transistor base is extracted from the substrate and repositioned to the source region. This extraction allows the base voltage to be controlled independently through the source line rather than through substrate potential, significantly improving voltage control precision and reducing disturbances to adjacent cells.
3Power
If high voltage is applied to bit line for write operation, then the charge injection is achieved, but the cell and nearby memory cells are damaged or disrupted
Solution Approach 1:
The source region serves as an intermediary structure with dual function: as the FET source and as the bipolar base. When writing data, the bipolar transistor injects charges into the floating body through the source region, enabling write operations at lower voltages and preventing damage to the cell and adjacent memory cells.
Solution Approach 2:
The patent replaces the conventional high-voltage direct injection method with a bipolar transistor-based charge injection mechanism. The bipolar transistor uses minority carrier injection through the source base junction, which achieves charge injection at lower voltages compared to direct high-voltage application to the bit line.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the surface area of memory cells, lowers the voltage requirements for write operations, and minimizes disturbances between adjacent cells, enhancing the reliability and efficiency of memory cell arrays while reducing power consumption and peripheral circuit complexity.
Implementation Method 1
the floating body uses an impact ionization phenomenon to store charges, which modifies the threshold voltage of the transistor
Data Source
AI summary
The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar transistor having an emitter, a base and a collector formed by the body of the FET transistor. Specifically, in the memory cell, the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor. The invention also includes a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to methods of controlling such memory cells.