FinFET Metal Gate Edge Removal for Parasitic Capacitance
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Solution Overview
Problem
Existing manufacturing methods for fin field-effect transistors face challenges in achieving a balance between proper filling windows for the work function layer and minimizing parasitic capacitance, leading to issues with device yield and performance due to excessive or insufficient removal of polysilicon gate ends.
Innovation Solution
The method involves forming a plurality of fins on a semiconductor substrate with a shallow trench filled with a first field oxide, followed by the formation of polysilicon gates that intersect with the fins, and then replacing these with metal gates, where the edge regions of the metal gates that protrude are removed to form a groove filled with a dielectric layer, thereby minimizing parasitic capacitance while maintaining a sufficient process window for the work function layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the edge region of metal gates is removed to minimize parasitic capacitance, then device performance is improved, but the process window for work function layer formation may be affected
Solution Approach 1:
The patent performs the edge region removal of metal gates after the work function layer has been formed, rather than before. This preliminary sequencing ensures that the work function layer process window is maintained while still achieving parasitic capacitance minimization through subsequent edge removal. The key insight is to establish the work function layer first, then remove the protruding edge regions of metal gates that would otherwise create parasitic capacitance with source/drain regions.
2Reliability
If existing manufacturing methods are used, then the work function layer can be formed, but parasitic capacitance cannot be minimized effectively
Solution Approach 1:
The patent extracts or removes the protruding edge regions of metal gates that extend beyond the fin region. By taking out these specific edge portions, the patent eliminates the source of parasitic capacitance between the gate and source/drain regions while preserving the main gate structure needed for device operation. This selective removal addresses the harmful parasitic capacitance without compromising the work function layer formation or overall device reliability.
Data Source
AI summary
A method for manufacturing a fin field-effect transistor is provided, comprising making metal gates, a gate dielectric layer, and a work function layer of the metal gate structures, followed by removing a portion of the end of each of the metal gates that protrudes from a fin region. Since the work function layer is already formed by the removing step, the process window of the work function layer is not affected. Therefore, a relatively large edge region of the metal gates can be removed, thereby minimizing the parasitic capacitance Cgs between the gate and the source or parasitic capacitance Cgd between the gate and the drain of a fin field-effect transistor device in operation. Meanwhile this step simplifies and compatible with the finFET process.