3D Memory Array With Gating Transistor For Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory arrays face challenges such as unstable performance, limited nonlinearity, and significant leakage current, which hinder their practical application, especially in three-dimensional integration.
Innovation Solution
A three-dimensional memory array is designed with memory cells connected to word lines and bit lines, featuring a gating transistor at the bottom of each word line, and the state of the memory cell is controlled through the bit line, word line, source line, and gate line, reducing nonlinear requirements and improving storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 1T1R structure with transistor as gating unit is used, then leakage current is suppressed, but memory cell area increases and three-dimensional stacking capability is reduced
Solution Approach 1:
The patent transitions from planar 1T1R structure to a three-dimensional stacked architecture where memory cells are arranged vertically across multiple layers. Word lines extend vertically through multiple memory cell layers, enabling leakage suppression without increasing lateral footprint, thus resolving the contradiction between reliability and area efficiency.
Solution Approach 2:
The word line serves multiple functions: it acts as a bit line for selected memory cells in one layer while simultaneously serving as a word line for memory cells in other layers. This multi-functionality reduces the total number of interconnect lines needed, decreasing area overhead while maintaining leakage suppression capabilities.
2Area of moving object
If 1S1R two-terminal structure is used, then area is reduced and scalability is improved, but selector material complexity increases and device performance fluctuates
Solution Approach 1:
The patent modifies the selector device structure by introducing a dual-gate configuration where the first gate is formed on the sidewall and the second gate is formed on the top surface. This structural parameter change enables better control over device performance and reduces sensitivity to material variations, addressing the performance fluctuation issue while maintaining area efficiency.
Solution Approach 2:
The patent introduces an intermediate electrode between the RRAM and selector that serves as a gateway electrode. This intermediary structure simplifies the overall device architecture and provides better interface control, reducing the complexity associated with selector material systems while maintaining the benefits of the 1S1R structure.
3Productivity
If conventional memory array architecture is used, then data transfer between processor and memory is enabled, but energy consumption increases and time delays occur
Solution Approach 1:
The patent implements a three-dimensional stacked memory architecture where multiple memory cell layers are vertically integrated with shared word lines. This vertical stacking enables higher storage density without increasing lateral area, and the shared interconnect structure reduces the total capacitance that needs to be charged/discharged, thereby lowering energy consumption while maintaining data transfer capability.
Data Source
AI summary
The present disclosure provides a three-dimensional memory array and a preparation method thereof, wherein the three-dimensional memory array includes memory cells arranged in an array; wherein in each memory cell: one end of the memory cell is connected to a word line WL, and the other end thereof is connected to a bit line BL; a corresponding gating transistor is arranged at the bottom of each word line WL, and the bottom of the word line WL is connected to the drain of the gating transistor; the gate of the gating transistor is connected to a gate line GL, and the source of the gating transistor is connected to a source line SL; the bit line BL, the word line WL, the source line SL and the gate line GL control the state of the memory cell.