Digital Storage TRIZ Cases

Segmented content-addressable memories enable high-speed keyword searches while minimizing memory capacity increases.

Segmented local bitlines route write current through selection circuits, reducing core layout area while maintaining reliable phase-change state transitions.

Dynamic write pulse width adjustment resolves suboptimal dynamic write margin across PVT conditions in conventional LUTRAM data write schemes.

Segmented local bit lines with ripple buffers reduce current leakage while maintaining storage capacity in advanced semiconductor processes.

A FIFO circuit synchronizes data transfer between memory controller and PHY clock domains using separate write and read pointers to maintain timing sequences.

A three-dimensional memory array uses a gating transistor at the word line bottom to control cell states and enhance storage capacity.

MOS transistor-based stabilizing circuits regulate current flow to prevent resistance oscillation during set and reset operations.

A sense amplifier with a reference signal providing unit and internal sense amplification unit processes data signals from memory cell arrays.

Rectangular diffusion regions enable shared source drain nodes across transistors with varying gate widths.

A magnetic memory structure uses voltage-controlled anisotropy to reduce write current and charge during data operations.

A self-timed memory design uses a common timing control circuit to simplify clock driver topology and improve synchronization.

A memory cell stores multiple bits by varying write pulse polarity and magnitude across a selector device and memory element.

A memory system stabilizes source voltage during power-down to enable controlled data write-back operations.

Adjusting current levels during read operations determines memory cell robustness against aging and temperature effects.

A crossbar array performs matrix-vector multiplications using programmable resistive elements and access elements.

A memory system uses holding circuits to store data addresses within nonvolatile cells, enabling direct retrieval without external microcomputer intervention.

A semiconductor memory controller manages data buffers to route information through available paths.

Sequential post pulses accelerate resistance drift in resistive memory cells, reducing programming duration and improving speed.

A memory device uses a sense amplifier connected to multiple bit lines and transistors for controlled data transmission.

A compute-in-memory apparatus integrates storage and computing functions within a single array to reduce transistor count.

Dual FIFOs decouple data and address storage from WDQS timing, resolving signal edge overlap that causes packet misinterpretation at 1 GHz.

A buffer system secures stabilization time for resistive memory cells to manage data integrity.

An active control unit adjusts drivability of output driver transistors via boosted voltages to reduce standby current.

A memory repair circuit switches between power supplies to store failed bit cell information during system shutdown.

A self-aligned pad layer with a protrusion extends along an active region side surface to electrically connect to bit lines.

Ferromagnetic and antiferromagnetic coupling in a magnetization induction unit sets diverse pinned layer directions using a single external field.

Separate bitline voltages prevent unwanted current flow between shared transistor components, resolving data integrity issues during high-density operations.

Word line control circuit manages voltage levels to activate SRAM cells using a single power supply, resolving element variations without increasing cell size.

A two-cycle sensing method isolates read current from leakage noise in memory arrays.

A word line level fixing circuit sets storage device word lines to a fixed potential upon memory cell power activation.

A memory storage circuit uses resistive elements to retain logic data without power supply.

A Correlated Electron Switch uses Mott transitions to enable scalable non-volatile memory operations with high density.

A memory cell uses a segmented variable resistance element and switching element to control read operations via voltage states.

A power management IC adjusts supply voltage capabilities based on refresh operation timing signals, reducing standby power consumption.

Stacked phase change memory cells with dual switches reduce leakage current and failure rates by enabling precise threshold voltage tuning.

Stacked semiconductor chips implement data bit inversion via through-silicon vias to minimize current consumption during high-speed data transmission.

Segmented DIMM enablement identifies faulty modules via PWR_GOOD signals, preventing boot failures and reducing troubleshooting time.

Vertical pin stacking and ground coupling eliminate cross-talk noise in DRAM data lines.

An auto refresh buffer controller detects data training requirements and generates enable signals to minimize operating current consumption in memory devices.

Position-dependent transmission line resistance compensates for parasitic variations, ensuring uniform bias current and voltage across all memory cells.

A sense amplifier dummy circuit provides a replica of the active state to time-vary power supply voltages for precise over-drive control.

A spin-orbit torque magnetoresistive memory structure forms the magnetic tunneling junction before the conductive channel layer.

A memory test system compares stored refresh address information against expected values to verify device functionality.

Precharging the access line via a shared sense amplifier cancels offset voltages, ensuring accurate memory cell state detection.

A clock synchronizer disables local clock signals during self-refresh exit, preventing NBTI degradation and spurious data transmission.

A dual voltage memory circuit design merges level shifting with decoder logic to reduce chip area and power consumption.

Opposite polarity voltage pulses reduce threshold-hold differences in selector devices, suppressing snapback without increasing device scale.

A semiconductor circuit outputs remaining repair information to a host for controlling post-packaging memory cell repairs.