Dynamic Power Supply Voltage Control for DRAM Refresh Operations

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Solution Overview

Problem

Current memory systems face inefficiencies in power management, particularly in standby mode, where DRAMs require periodic refresh operations, leading to unnecessary high power supply capabilities due to the inability to distinguish between refresh and non-refresh periods, resulting in increased power consumption.

Innovation Solution

The integration of a controller and power management IC that dynamically adjusts the power supply voltage capabilities based on the refresh operation timing, using an enable signal RefEN to notify the power management IC when a refresh operation is occurring, allowing for reduced power consumption by setting the supply capability to a middle or low level during non-refresh periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the power supply capability is set to a high level to ensure sufficient power during refresh operations, then the reliability of memory cell data retention is improved, but the power consumption increases during standby mode

Engineering Contradiction:

Improvedata retention reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The power supply capability is made dynamically adjustable rather than fixed. The power management IC switches between a first power supply capability (higher level) during refresh operations and a second power supply capability (lower level) during non-refresh periods, allowing the system to adapt power delivery to actual operational needs and reduce unnecessary power consumption during standby mode

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the power supply capability parameter based on operational state. By detecting refresh operation timing and adjusting the power supply capability accordingly, the system transitions between different power delivery levels to match the actual power requirements of the memory device during refresh versus standby periods

Inventive Principle:

Principle #35Parameter changes

2Device complexity

If the power management IC size is reduced to minimize system footprint, then the device complexity is reduced, but the ability to provide sufficient power during refresh operations may be compromised

Engineering Contradiction:

Improvepower management IC sizeVSAvoidpower supply capability

Core Design Contradiction:

Device complexityVSPower

Solution Approach 1:

The power management IC incorporates dynamic power supply capability adjustment that allows a smaller device to deliver higher power when needed. By switching between different power supply capabilities based on refresh operation timing, a compact PMIC can provide sufficient power during brief refresh periods while maintaining a smaller overall size and reducing system footprint during standby mode

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11250903B2Apparatus for supplying power supply voltage to semiconductor chip including volatile memory cell

Publication Date: 2022.02.15 MICRON TECHNOLOGY INC

AI summary

Disclosed herein is an apparatus that includes a first semiconductor chip including a memory cell array having a volatile memory cell and an access control circuit configured to perform a refresh operation on the volatile memory cell, and a second semiconductor chip including a power generator configured to supply a first power supply voltage to the first semiconductor chip. The access control circuit is configured to activate a first enable signal during the refresh operation. The second semiconductor chip is configured to change a capability of the power generator based on the first enable signal.