FIFO Circuit Synchronizes DDR Memory Clock Domains
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Solution Overview
Problem
In conventional DDR memory systems, it is challenging to maintain the specified timing sequence relationship between write and read commands and data due to the difficulty in designing a suitable DFI clock tree root, leading to potential data loss or erroneous operation of the DDR memory.
Innovation Solution
A FIFO circuit is introduced, comprising a pointer generator and a FIFO buffer, which operates between the memory controller and the physical layer circuit, using separate reference clocks for write and read operations to synchronize data transfer and maintain the timing sequence, allowing the memory controller to operate in the main clock domain while the PHY circuit operates in the DFI clock domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the memory controller and PHY circuit operate in the same DFI clock domain, then clock synchronization is simplified, but it becomes impossible to design a suitable DFI clock tree root when CMD PHY and data PHY are allocated at different positions, leading to timing sequence relationship violations
Solution Approach 1:
The patent divides the clock domain into two separate domains: the memory controller operates in the main clock domain while the PHY circuit operates in the DFI clock domain. This segmentation allows each component to use its own optimal clock source without interfering with the other, resolving the contradiction between clock tree design simplicity and timing relationship reliability.
Solution Approach 2:
The FIFO circuit acts as an intermediary between the main clock domain and the DFI clock domain. It includes a write pointer generated by the main clock and a read pointer generated by the DFI clock, which coordinate data transfer between the two domains while maintaining the required timing sequence relationships.
2Adaptability or versatility
If separate clock domains are used for memory controller and PHY circuit, then clock tree design flexibility is improved, but data transfer synchronization between domains becomes challenging
Solution Approach 1:
The FIFO buffer serves as an intermediary storage mechanism between the two clock domains. The write pointer (operating in main clock domain) and read pointer (operating in DFI clock domain) coordinate access to the FIFO buffer, enabling seamless data transfer while maintaining synchronization despite the separate clock domains.
Solution Approach 2:
The patent changes the clock frequency parameter between domains by using a phase-locked loop (PLL) to generate the DFI clock from the main clock. This allows the system to adapt to different clock frequencies while maintaining proper timing relationships through the FIFO synchronization mechanism.
Data Source
AI summary
A FIFO circuit for a DDR memory system includes a pointer generator and a FIFO circuit. The FIFO circuit includes a pointer generator and a FIFO buffer. The pointer generator receives a first reset signal and a delay select signal from the memory controller. After the first reset signal is de-asserted, the pointer generator generates a write pointer according to a first reference clock and the pointer generator generates a read pointer according to a second reference clock. An input data is stored into the FIFO buffer according to the first reference clock and the write pointer. An output data is outputted from the FIFO buffer according to the second reference clock and the read pointer.