Compute-in-Memory SRAM Cell Area Efficiency via Bit Line Boost

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Solution Overview

Problem

Current compute-in-memory designs face challenges with area efficiency and power consumption due to the limitations of Static Random-Access Memory (SRAM) and emerging non-volatile memories, leading to increased energy consumption and latency in edge AI applications, particularly in large-scale neural networks.

Innovation Solution

A compute-in-memory apparatus comprising a computing array with storage cells and reset switches, along with capacitors, that utilize a control module to perform operations such as multiply-and-accumulate and logic AND operations, improving area efficiency by reducing the number of transistors required and enabling multi-bit storage with a single storage switch.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If 6T SRAM cells are used for computing, then the cell area is reduced, but the swing range of bit line voltage is limited leading to read disturbance and small signal margin

Engineering Contradiction:

ImproveSRAM cell areaVSAvoidread disturbance and signal margin

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent changes the operating voltage parameters by introducing a bit line boost circuit that dynamically adjusts the bit line voltage during read operations. This allows the system to use compact 6T SRAM cells while maintaining adequate signal margins by boosting the bit line voltage to enhance the read signal strength without increasing the cell area.

Inventive Principle:

Principle #35Parameter changes

2Speed

If SRAM-based compute-in-memory is used, then fast read/write speed is achieved, but area efficiency is insufficient for large neural networks

Engineering Contradiction:

Improveread/write speedVSAvoidcompute cell area

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The patent merges the storage function and compute function into a single integrated structure where 6T SRAM cells perform both storage and computing operations. By combining these functions and using the storage nodes directly as compute elements, the design achieves fast read/write speeds while improving area efficiency compared to separate storage and compute units.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent makes the 6T SRAM cell multi-functional by enabling it to perform both storage operations and computing operations (such as in-memory computing for neural network operations). This universality allows the same hardware structure to serve multiple purposes, improving area efficiency while maintaining the fast speed characteristics of SRAM.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If more transistors are used in SRAM for computing, then voltage swing range is improved, but area efficiency is reduced

Engineering Contradiction:

Improvevoltage swing rangeVSAvoidcompute cell area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent introduces a bit line boost circuit as an intermediary component that mediates between the compact 6T SRAM cell and the read operation requirements. This boost circuit actively adjusts the bit line voltage to provide sufficient voltage swing range for reliable reading, eliminating the need to increase the number of transistors in the SRAM cell itself while still achieving the required voltage characteristics.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Loss of energy

If compute-in-memory integrates storage and computation, then data movement is reduced, but device complexity increases

Engineering Contradiction:

Improveenergy consumptionVSAvoidsystem complexity

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The patent segments the compute-in-memory system into standardized 6T SRAM cell units with associated control circuits. By dividing the system into modular, repeating units rather than using a monolithic complex structure, the design achieves integration of storage and computation while managing device complexity through systematic segmentation and reuse of basic building blocks.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20240005977A1Compute-in-memory devices, neural network accelerators, and electronic devices

Publication Date: 2024.01.04 TSINGHUA UNIVERSITY

AI summary

The disclosed apparatus comprises a computing array comprising a plurality of computing modules, wherein each computing module comprises at least one storage cell, a reset switch, and a capacitor; the storage cell comprises at least one storage switch, and the storage switch comprises a storage control terminal, a storage detection terminal, and a storage terminal, the storage control terminal to receive a storage state voltage to adjust the impedance characteristic between the storage detection terminal and the storage terminal; the reset switch comprises a reset control terminal, a reset detection terminal, and a reset terminal, the reset control terminal to receive a reset voltage and the reset terminal is used to receive a reset state voltage. The disclosed apparatus also comprises a control module, which is used to control the computing array to perform at least one of a store operation, a read operation, and a compute operation.