Multi-Level Memory Cell Using Polarity and Magnitude Control
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Solution Overview
Problem
Traditional memory cells in cross-point architecture are limited to storing a single bit per cell, restricting storage capacity without increasing the memory array area.
Innovation Solution
A memory cell configuration that includes a memory element and a selector device, utilizing both to store multiple bits by varying the magnitude and polarity of voltage and current applied during write pulses, allowing for multiple threshold voltages corresponding to different logic states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional memory cells in cross-point architecture are used, then the structure is simple and easy to manufacture, but the storage capacity is limited to one bit per cell
Solution Approach 1:
The patent applies parameter changes by utilizing multiple threshold voltage states of the memory element. By controlling the resistance of the memory element to exhibit different threshold voltages (first, second, third threshold voltages), the memory cell can store multiple bits of data. This transforms a binary storage system into a multi-level storage system, increasing storage capacity without requiring additional memory cells.
Solution Approach 2:
The patent implements multi-functionality by enabling the same memory cell structure to perform both single-bit and multi-bit storage functions. The memory element can operate in different modes (different resistance states) to store different amounts of data, making the memory cell universal for various storage requirements without changing the basic cross-point architecture.
2Quantity of substance
If multiple bits are stored per memory cell, then storage capacity increases, but the complexity of writing and reading operations increases
Solution Approach 1:
The patent applies segmentation by dividing the data storage into multiple distinct threshold voltage levels. Each threshold voltage (first, second, third threshold voltages) represents a separate state that can be independently controlled and read. This segmentation of the voltage spectrum into discrete levels simplifies the reading operation, as each level can be detected independently to determine the stored data bits.
Solution Approach 2:
The patent utilizes feedback mechanisms in the control circuitry to manage the complex writing operations. The control circuit receives data to be written, determines the appropriate threshold voltage state based on the data values, and applies the corresponding voltages to the memory element. This feedback-controlled approach simplifies the interface between the control logic and the physical memory element, making the operation easier despite the multi-bit storage complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables storage of multiple bits per cell, increasing storage capacity without expanding the memory array area, through the use of phase change materials and chalcogenide materials in the memory element and selector device, allowing for efficient writing and reading protocols.
Implementation Method 1
The memory element may include a phase change material
Implementation Method 2
The memory element and selector device may be located at a cross-point of a first access line
Implementation Method 3
The selector device may reduce leakage currents and allow selection of a single memory element
Data Source
Figure 1A
Figure 1B
Figure 2
AI summary
Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.