Resistive Memory Bitline Voltage Control for Density
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Solution Overview
Problem
The scaling of dynamic random access memory (DRAM) technology is limited by retention time issues, and existing resistive memory devices face challenges in achieving higher memory density due to the use of a single access transistor for multiple resistive memory components, which can lead to unwanted current flow and data corruption.
Innovation Solution
A memory device and method that utilize multiple resistive memory components sharing a single access transistor, with bitline controllers applying different voltages to separate sets of bitlines to manage current flow and prevent data corruption, ensuring that only intended resistive memory components are written to by meeting or exceeding a threshold voltage on one set of bitlines while maintaining the state of another set below the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple resistive memory components share a single access transistor to increase memory density, then memory density is improved, but unwanted current flow and data corruption occur
Solution Approach 1:
The patent divides the bitline control into separate segments by providing individual bitline controllers for different sets of bitlines. Each controller independently manages voltage levels for its associated bitlines, enabling selective activation of specific resistive memory components while preventing unwanted current flow to other components sharing the same access transistor.
Solution Approach 2:
The patent applies different voltage levels to different sets of bitlines based on local requirements. The bitline controller applies a first voltage level to bitlines connected to target resistive memory components for read/write operations, while applying a second voltage level to bitlines connected to non-target components, thereby preventing unwanted current flow in specific local regions.
2Device complexity
If a single access transistor controls multiple resistive memory components, then device complexity is reduced, but current flow control precision deteriorates
Solution Approach 1:
The patent introduces bitline controllers as intermediary devices between the control logic and the resistive memory components. These controllers act as mediators that precisely regulate voltage levels on individual bitlines, enabling fine-grained control of current flow to each resistive memory component even when they share a common access transistor.
Solution Approach 2:
The patent implements dynamic voltage control where the bitline controllers continuously adjust voltage levels on bitlines based on operation requirements. During read/write operations, the controllers dynamically switch between different voltage levels to enable or disable current flow to specific resistive memory components, providing temporal control precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient read and write operations across multiple resistive memory components, reducing unwanted current flow and data corruption, thereby enhancing memory density and reliability.
Implementation Method 1
resistive memory components each designed to store data as resistance... applying a first voltage to a first set of the plurality of bitlines and a second voltage to a second set of bitlines
Data Source
AI summary
Embodiments of the present disclosure describe a device and methods of accessing the device. The device can include a plurality of memory cells, each cell including a plurality of resistive memory components each designed to store data as resistance and an access transistor configured to control access to the plurality of resistive memory components. A wordline is configured to enable access to the set of resistor memory components by enabling the access transistor. A plurality of bitlines are each connected to a respective and different set of resistive memory components from each of the plurality of memory cells. A bitline controller is configured to access the plurality of resistive memory components by applying a first voltage to a first set of the plurality of bitlines and a second voltage to a second set of bitlines.