Self-Timed Memory Common Timing Control Circuit
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Solution Overview
Problem
Existing self-timed memory clock timing circuits face challenges in meeting timing requirements at higher clock speeds due to complex logic circuits in the critical timing path and multiple independent timing paths, which increase complexity and risk of incorrect clock recovery.
Innovation Solution
A self-timed memory design with a common timing control circuit that removes complex logic circuits from the critical timing path, separates the clock timing path from the clock latch control path, and uses shared clock driver circuits to improve synchronization and reduce the risk of incorrect clock initialization, thereby simplifying circuit topology and enhancing critical timing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple independent clock driver circuits are used for different timing paths, then the memory can control different operations (read, write, address latching), but the circuit complexity increases and the risk of incorrect clock recovery increases
Solution Approach 1:
The patent merges multiple independent clock driver circuits into a single shared clock driver circuit that serves all timing paths (read, write, address latching, decoder timing). This consolidation reduces circuit complexity while maintaining the ability to control different operations through a single unified timing mechanism that generates all necessary clock signals from one source.
Solution Approach 2:
The single clock driver circuit is designed to perform multiple functions by generating different clock signals (CLK_READ_B, CLK_WRITE_B, CLK_ADDR_B, CLK_DEC_B) for different operations. This universal timing control mechanism eliminates the need for separate dedicated clock drivers for each operation, thereby reducing complexity while preserving operational versatility.
2Manufacturing precision
If complex logic circuits are placed in the critical timing path, then the memory can implement precise timing control, but the speed performance deteriorates at higher clock frequencies
Solution Approach 1:
The patent extracts complex logic circuits from the critical timing path by implementing timing control through a simplified single clock driver circuit that generates timing signals directly without passing through complex logic gates. This extraction removes the bottleneck that limited speed performance, allowing the memory to operate at higher clock frequencies while maintaining timing precision through the unified clock signal generation approach.
3Ease of operation
If separate latch control paths are used for each clock driver, then each path can be independently controlled, but the risk of incorrect clock initialization increases
Solution Approach 1:
The patent merges all latch control paths into a single shared latch control mechanism that manages the reset latch for all clock driver circuits. This unified control approach ensures that all clock signals are initialized and recovered correctly through a single coordinated process, eliminating the risks associated with multiple independent control paths while maintaining operational flexibility.
Data Source
AI summary
A memory comprises a memory array and a plurality of clock driver circuits for providing a plurality of clock driver signals for timing an access to the memory array. A timing control circuit is coupled to the plurality of clock driver circuits. The timing control circuit includes a latch that is coupled to each of the plurality of clock driver circuits. The latch is for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to a first predetermined edge of a clock signal. The timing control circuit removes complex logic gates from the clock critical timing paths. Also, circuit topology is simplified allowing improved critical timing performance. Also, all of the clock driver circuits share a common latch control to improve clock recovery synchronization and reduce a risk of initializing the clock timing circuit in the wrong logic state.