Buffer Control Circuit for Memory Data Training Power

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Solution Overview

Problem

Conventional memory devices experience increased current consumption during auto-refresh mode due to the enabling of data input/output buffers, even when no data training operation is performed, leading to inefficiencies in power management.

Innovation Solution

A buffer control circuit that selectively enables data input/output buffers only during data training operations in auto-refresh mode and disables them in low power mode or when no data training is performed, using an auto-refresh buffer controller to generate an enable control signal for the buffers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data input/output buffers are enabled during auto-refresh mode, then data training operation can be performed, but current consumption increases

Engineering Contradiction:
Improvedata training operation capabilityVSAvoidcurrent consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the buffer enable/disable state changeable based on operational mode. The buffer controller dynamically adjusts buffer states according to whether auto-refresh mode is active and whether data training is required, transitioning between enabled and disabled states to optimize power consumption while maintaining operational capability when needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameter of buffer enable/disable state based on mode conditions. By detecting auto-refresh mode and determining whether data training is required, the system changes the buffer state parameter from enabled to disabled or vice versa, thereby controlling current consumption while preserving data training capability when necessary.

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If data input/output buffers are disabled during auto-refresh mode, then current consumption is reduced, but data training operation cannot be performed

Engineering Contradiction:
Improvecurrent consumptionVSAvoiddata training operation capability
Core Design Contradiction:
Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The system dynamically adjusts buffer states based on real-time operational requirements. When auto-refresh mode is detected and data training is determined to be unnecessary, buffers are disabled to reduce power consumption. When data training is required, buffers are enabled, providing adaptive response to changing operational conditions and maintaining versatility.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The buffer enable/disable parameter is changed based on detected operational mode and training requirements. The system monitors mode signals and changes the buffer state parameter accordingly, enabling buffers only when data training is needed and disabling them during normal auto-refresh operations to optimize power efficiency.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If all data input/output buffers are enabled during auto-refresh mode, then system is ready to receive data, but current consumption increases

Engineering Contradiction:
Improvedata reception readinessVSAvoidcurrent consumption
Core Design Contradiction:
Ease of operationVSUse of energy by moving object

Solution Approach 1:

Instead of enabling all buffers continuously, the patent applies partial action by enabling only the specific buffers required for data training operations during auto-refresh mode. The buffer controller selectively activates buffers based on actual training needs, avoiding the excessive action of keeping all buffers enabled and thereby reducing unnecessary power consumption while maintaining operational readiness when needed.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS7961528B2Buffer control circuit of memory device
Publication Date: 2011.06.14 SK HYNIX INC
  • US7961528B2 patent drawing
  • US7961528B2 patent drawing
  • US7961528B2 patent drawing

AI summary

A buffer control circuit of a memory device has an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller.