Memory Clock Synchronizer for NBTI Degradation
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Solution Overview
Problem
Memory devices, such as DRAM, face negative-bias temperature instability (NBTI) during self-refresh mode, leading to transistor degradation and spurious data transmission when switching from self-refresh to normal operation due to residual artifacts in clock signals.
Innovation Solution
The implementation of a clock synchronizer and command mask circuit within the internal clock circuit of a semiconductor device, which disables the local clock signal and delays command processing upon exiting self-refresh mode, ensuring the clock signal is cleaned up before resuming normal operations, thereby preventing NBTI degradation and erroneous data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the memory device enters self-refresh mode to reduce power consumption, then power savings are achieved, but NBTI degradation occurs in transistors due to prolonged negative gate-to-source voltage
Solution Approach 1:
The patent applies periodic action by toggling the gate-to-source voltage of transistors during self-refresh mode at specific intervals. This periodic voltage switching prevents NBTI degradation by periodically relieving the negative bias stress on the transistor gates, while still maintaining the low-power self-refresh state. The toggling occurs synchronously with refresh operations to prevent data loss.
2Reliability
If signal toggling is used to avoid NBTI during self-refresh, then transistor degradation is reduced, but spurious artifacts remain in the clock signal when transitioning to normal operation
Solution Approach 1:
The patent applies preliminary action by preparing the clock signal in advance before mode transition. A synchronized clock signal is generated that is aligned with the toggling of refresh signals during self-refresh mode. This preliminary synchronization ensures that when transitioning to normal operation, the clock signal is already in a clean state without spurious artifacts, preventing erroneous data transmission.
Solution Approach 2:
The patent uses an intermediary synchronized clock signal that mediates between the toggling refresh signals and the normal operation clock. This intermediate clock signal absorbs the toggling artifacts and presents a clean clock signal to the rest of the system, preventing spurious data transmission during mode transitions.
3Reliability
If the clock signal is continuously toggled during self-refresh to prevent NBTI, then transistor reliability is improved, but data integrity may be compromised due to residual artifacts
Solution Approach 1:
The patent applies local quality by making the clock signal characteristics location-dependent and mode-dependent. During self-refresh mode, the clock signal is synchronized with refresh toggling to protect transistors. When transitioning to normal operation, the clock signal automatically switches to a non-toggling state to ensure data integrity. This local adaptation of clock signal properties resolves the conflict between transistor protection and data integrity.
Data Source
AI summary
An apparatus may include a semiconductor device that includes an internal clock circuit configured to receive an internal clock signal and to provide a local clock signal based on the internal clock signal. The internal clock circuit comprises a clock synchronizer configured to, in response to receipt of a command to exit a self-refresh mode, disable provision of the local clock signal by a number of cycles of the internal clock signal.