FeRAM Power-Down Data Retention via Write-Back Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ferroelectric random access memory (FeRAM) experiences data loss due to its destructive read nature, where data is not retained during power-down events before rewriting can occur, leading to data destruction and loss.
Innovation Solution
The implementation of a memory system with a CKE pin-based power-down notification and a stabilization capacitance, along with controlling units and buffers, ensures that data is written back to the memory cell after a predetermined time following power-down notification, preventing data loss by maintaining the source voltage and enabling controlled write-back operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If FeRAM uses destructive read operation to read data, then read operation can be performed, but data is destroyed and lost during power-down events before rewrite can occur
Solution Approach 1:
The patent applies preliminary action by implementing a power-down detection mechanism that activates before actual power-down occurs. The detection circuit monitors voltage levels and triggers a write-back operation in advance, transferring data from the ferroelectric capacitor to a storage register before power is completely lost. This prevents data destruction by performing the protective write-back action preliminarily, before the harmful power-down event completes.
Solution Approach 2:
The patent uses an intermediary approach by introducing a storage register as a buffer between the ferroelectric capacitor and the external interface. During power-down events, data is temporarily transferred to this intermediary storage register, which maintains data even when power is lost. The storage register acts as a mediator that protects data from the destructive effect of power-down, allowing data to be preserved and later restored to the capacitor when power is restored.
2Reliability
If data is written back immediately after power-down notification, then data loss can be prevented, but data may not be fully transferred and written back completing the operation
Solution Approach 1:
The patent applies dynamics by implementing a timing mechanism that dynamically adjusts the write-back operation based on system state. Rather than using a fixed immediate write-back, the system monitors whether the write-back operation has completed before allowing power-down to proceed. The control logic dynamically determines when to permit power-down based on the completion status of data transfer, ensuring data integrity while managing the timing flexibility needed for complete operation execution.
3Use of energy by moving object
If power-down is allowed to occur during read operation, then power consumption can be reduced, but data remains destroyed and is lost
Solution Approach 1:
The patent applies preliminary anti-action by implementing a power-down detection circuit that monitors for power-down conditions and triggers a counteracting write-back operation. When power-down is detected, the system automatically initiates data transfer from the ferroelectric capacitor to the storage register, counteracting the potential data loss. This preliminary protective action occurs automatically upon detecting power-down conditions, preventing data loss while allowing power-down to occur for energy savings.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents data loss during power-down events by ensuring that all data is transferred and written back to the memory cell, enhancing data maintainability and reliability in FeRAM systems.
Implementation Method 1
a memory cell including a ferroelectric capacitor and a cell transistor
Implementation Method 2
the implementation of a memory system with a CKE pin-based power-down notification and a stabilization capacitance
Data Source
AI summary
In one embodiment, a non-volatile memory includes a first buffer that receives notification of power-down and outputs a first signal changed from a first value to a second value based on the notification, a first controlling unit that receives and outputs a command signal, a second controlling unit that generates and outputs a basic signal that has a third value when the command signal output from the first controlling unit indicates an active command and has a fourth value when the command signal indicates a command corresponding to a write back instruction or the first signal has the second value, a memory cell array in which memory cells are arrayed, and a sense amplifier circuit that reads data from the memory cell.